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[/] [z80soc/] [branches/] [RonivonCosta/] [S3E/] [lcdvram.vhd] - Blame information for rev 31

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--------------------------------------------------------------------------------
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--     This file is owned and controlled by Xilinx and must be used           --
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--     solely for design, simulation, implementation and creation of          --
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--     design files limited to Xilinx devices or technologies. Use            --
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--     with non-Xilinx devices or technologies is expressly prohibited        --
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--     and immediately terminates your license.                               --
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--                                                                            --
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--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
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--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
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--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
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--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
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--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
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--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
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--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
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--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
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--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
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--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
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--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
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--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
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--     FOR A PARTICULAR PURPOSE.                                              --
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--                                                                            --
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--     Xilinx products are not intended for use in life support               --
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--     appliances, devices, or systems. Use in such applications are          --
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--     expressly prohibited.                                                  --
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--                                                                            --
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--     (c) Copyright 1995-2007 Xilinx, Inc.                                   --
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--     All rights reserved.                                                   --
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--------------------------------------------------------------------------------
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-- You must compile the wrapper file lcdvram.vhd when simulating
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-- the core, lcdvram. When compiling the wrapper file, be sure to
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-- reference the XilinxCoreLib VHDL simulation library. For detailed
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-- instructions, please refer to the "CORE Generator Help".
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-- The synthesis directives "translate_off/translate_on" specified
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-- below are supported by Xilinx, Mentor Graphics and Synplicity
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-- synthesis tools. Ensure they are correct for your synthesis tool(s).
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- synthesis translate_off
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Library XilinxCoreLib;
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-- synthesis translate_on
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ENTITY lcdvram IS
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        port (
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        addra: IN std_logic_VECTOR(4 downto 0);
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        addrb: IN std_logic_VECTOR(4 downto 0);
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        clka: IN std_logic;
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        clkb: IN std_logic;
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        dina: IN std_logic_VECTOR(7 downto 0);
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        doutb: OUT std_logic_VECTOR(7 downto 0);
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        wea: IN std_logic);
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END lcdvram;
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ARCHITECTURE lcdvram_a OF lcdvram IS
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-- synthesis translate_off
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component wrapped_lcdvram
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        port (
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        addra: IN std_logic_VECTOR(4 downto 0);
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        addrb: IN std_logic_VECTOR(4 downto 0);
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        clka: IN std_logic;
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        clkb: IN std_logic;
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        dina: IN std_logic_VECTOR(7 downto 0);
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        doutb: OUT std_logic_VECTOR(7 downto 0);
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        wea: IN std_logic);
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end component;
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-- Configuration specification 
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        for all : wrapped_lcdvram use entity XilinxCoreLib.blkmemdp_v6_3(behavioral)
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                generic map(
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                        c_reg_inputsb => 0,
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                        c_reg_inputsa => 0,
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                        c_has_ndb => 0,
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                        c_has_nda => 0,
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                        c_ytop_addr => "1024",
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                        c_has_rfdb => 0,
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                        c_has_rfda => 0,
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                        c_ywea_is_high => 0,
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                        c_yena_is_high => 1,
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                        c_yclka_is_rising => 1,
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                        c_yhierarchy => "hierarchy1",
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                        c_ysinita_is_high => 1,
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                        c_ybottom_addr => "0",
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                        c_width_b => 8,
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                        c_width_a => 8,
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                        c_sinita_value => "0",
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                        c_sinitb_value => "0",
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                        c_limit_data_pitch => 18,
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                        c_write_modeb => 0,
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                        c_write_modea => 2,
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                        c_has_rdyb => 0,
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                        c_yuse_single_primitive => 0,
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                        c_has_rdya => 0,
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                        c_addra_width => 5,
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                        c_addrb_width => 5,
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                        c_has_limit_data_pitch => 0,
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                        c_default_data => "20",
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                        c_pipe_stages_b => 0,
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                        c_yweb_is_high => 0,
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                        c_yenb_is_high => 1,
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                        c_pipe_stages_a => 0,
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                        c_yclkb_is_rising => 1,
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                        c_yydisable_warnings => 1,
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                        c_enable_rlocs => 0,
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                        c_ysinitb_is_high => 1,
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                        c_has_web => 0,
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                        c_has_default_data => 1,
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                        c_has_sinitb => 0,
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                        c_has_wea => 1,
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                        c_has_sinita => 0,
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                        c_has_dinb => 0,
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                        c_has_dina => 1,
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                        c_ymake_bmm => 0,
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                        c_sim_collision_check => "NONE",
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                        c_has_enb => 0,
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                        c_has_ena => 0,
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                        c_depth_b => 32,
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                        c_mem_init_file => "mif_file_16_1",
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                        c_depth_a => 32,
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                        c_has_doutb => 1,
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                        c_has_douta => 0,
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                        c_yprimitive_type => "16kx1");
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-- synthesis translate_on
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BEGIN
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-- synthesis translate_off
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U0 : wrapped_lcdvram
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                port map (
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                        addra => addra,
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                        addrb => addrb,
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                        clka => clka,
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                        clkb => clkb,
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                        dina => dina,
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                        doutb => doutb,
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                        wea => wea);
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-- synthesis translate_on
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END lcdvram_a;
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