URL https://opencores.org/ocsvn/z80soc/z80soc/trunk

Subversion Repositories z80soc

[/] [z80soc/] [branches/] [RonivonCosta/] [S3E/] [top_s3e.vhd] - Blame information for rev 11

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-------------------------------------------------------------------------------------------------
-- Z80_Soc (Z80 System on Chip)
-- 
-- Version 0.5 Beta
--
-- Developer: Ronivon Candido Costa
-- Release Date: 2008 / 04 / 16
--
-- Based on the T80 core: http://www.opencores.org/projects.cgi/web/t80
-- This version developed and tested on: Altera DE1 Development Board
--
-- Peripherals configured (Using Ports):
--
--      08 KB Internal ROM      Read            (0x0000h - 0x1FFFh)
--      08 KB INTERNAL VRAM     Write           (0x2000h - 0x3FFFh)
--      48 KB External SRAM     Read/Write      (0x4000h - 0xFFFFh)
--      08 Green Leds                   Out             (Port 0x01h)
--      08 Red Leds                             Out             (Port 0x02h)
--      04 Seven Seg displays   Out             (Ports 0x10h and 0x11h)
--      36 Pins GPIO0                   In/Out  (Ports 0xA0h, 0xA1h, 0xA2h, 0xA3h, 0xA4h, 0xC0h)
--      36 Pins GPIO1                   In/Out  (Ports 0xB0h, 0xB1h, 0xB2h, 0xB3h, 0xB4h, 0xC1h)
--      08 Switches                             In              (Port 0x20h)
--      04 Push buttons                 In              (Port 0x30h)
--      PS/2 keyboard                   In              (Port 0x80h)
--      Video Out (VGA)                 Out             (0x2000h - 0x24B0)
--
--
--  Revision history:
--
-- 2008/04(21 - Ported to Spartan 3E
--
--      2008/04/17 - Added Video support for 80x40 mode
--  2008/04/16 - Release Version 0.5-DE1-Beta
--
-- TO-DO:
--      - Monitor program to introduce Z80 Assmebly codes and run
--      - Serial communication, to download assembly code from PC
--      - Add hardware support for 80x40 Video out
--      - SD/MMC card interface to read/store data and programs
-------------------------------------------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
 
entity Z80SOC_TOP is
  generic (
    swcount             : integer := 4;
         keycount       : integer := 4;
         ledrcount      : integer := 10;
         ledgcount      : integer := 8;
         sramdepth      : integer := 16;
         dramdepth      : integer := 13;
         framdepth      : integer := 25;
         vgadepth       : integer := 1);
        port(
    -- Clocks
    CLOCK_50 : in std_logic;                                    -- 50 MHz
 
    -- Buttons and switches
    KEY : in std_logic_vector(keycount - 1 downto 0);         -- Push buttons
    SW : in std_logic_vector(swcount-1 downto 0);          -- Switches
 
    -- LED displays
    LEDG : out std_logic_vector(ledgcount-1 downto 0);       -- Green LEDs
 
    -- RS-232 interface
    -- UART_TXD : out std_logic;                      -- UART transmitter   
    -- UART_RXD : in std_logic;                       -- UART receiver
 
    -- PS/2 port
    PS2_DAT,                    -- Data
    PS2_CLK : inout std_logic;     -- Clock
 
    -- VGA output
    VGA_HS,                                             -- H_SYNC
    VGA_VS : out std_logic;                             -- SYNC
    VGA_R,                                              -- Red[3:0]
    VGA_G,                                              -- Green[3:0]
    VGA_B : out std_logic;                                                                         -- Blue[3:0]
         SF_D  : out std_logic_vector(3 downto 0);
         LCD_E, LCD_RS, LCD_RW, SF_CE0 : out std_logic
);
end Z80SOC_TOP;
 
architecture rtl of Z80SOC_TOP is
 
        component clk_div
        PORT
        (
                clock_25Mhz                             : IN    STD_LOGIC;
                clock_1MHz                              : OUT   STD_LOGIC;
                clock_100KHz                    : OUT   STD_LOGIC;
                clock_10KHz                             : OUT   STD_LOGIC;
                clock_1KHz                              : OUT   STD_LOGIC;
                clock_100Hz                             : OUT   STD_LOGIC;
                clock_10Hz                              : OUT   STD_LOGIC;
                clock_1Hz                               : OUT   STD_LOGIC);
        end component;
 
        component T80s
        generic(
                Mode : integer := 0);
        port (
                RESET_n         : in std_logic;
                CLK_n           : in std_logic;
                WAIT_n          : in std_logic;
                INT_n           : in std_logic;
                NMI_n           : in std_logic;
                BUSRQ_n         : in std_logic;
                M1_n            : out std_logic;
                MREQ_n          : out std_logic;
                IORQ_n          : out std_logic;
                RD_n            : out std_logic;
                WR_n            : out std_logic;
                RFSH_n          : out std_logic;
                HALT_n          : out std_logic;
                BUSAK_n         : out std_logic;
                A                       : out std_logic_vector(15 downto 0);
                DI                      : in std_logic_vector(7 downto 0);
                DO                      : out std_logic_vector(7 downto 0));
        end component;
 
        component lcd
        port(
                clk, reset : in std_logic;
                SF_D : out std_logic_vector(3 downto 0);
                LCD_E, LCD_RS, LCD_RW, SF_CE0 : out std_logic;
                lcd_addr        : out std_logic_vector(4 downto 0);
                lcd_char        : in std_logic_vector(7 downto 0));
        end component;
 
        component lcdvram
        port (
                addra: IN std_logic_VECTOR(4 downto 0);
                addrb: IN std_logic_VECTOR(4 downto 0);
                clka: IN std_logic;
                clkb: IN std_logic;
                dina: IN std_logic_VECTOR(7 downto 0);
                doutb: OUT std_logic_VECTOR(7 downto 0);
                wea: IN std_logic);
        end component;
 
        component rom
        port (
                clk     : in std_logic;
                addr    : in std_logic_vector(12 downto 0);
                dout    : out std_logic_vector(7 downto 0));
        end component;
 
        component Clock_357Mhz
        PORT (
                clock_50Mhz                             : IN    STD_LOGIC;
                clock_357Mhz                    : OUT   STD_LOGIC);
        end component;
 
        component ps2kbd
        PORT (
                        keyboard_clk    : inout std_logic;
                        keyboard_data   : inout std_logic;
                        clock                   : in std_logic;
                        clkdelay                : in std_logic;
                        reset                   : in std_logic;
                        read                    : in std_logic;
                        scan_ready              : out std_logic;
                        ps2_ascii_code  : out std_logic_vector(7 downto 0));
        end component;
 
component vram
        port (
        addra: IN std_logic_VECTOR(10 downto 0);
        addrb: IN std_logic_VECTOR(10 downto 0);
        clka: IN std_logic;
        clkb: IN std_logic;
        dina: IN std_logic_VECTOR(7 downto 0);
        doutb: OUT std_logic_VECTOR(7 downto 0);
        wea: IN std_logic);
end component;
 
        COMPONENT video_80x40
        PORT(   CLOCK_50                : IN STD_LOGIC;
                        VRAM_DATA               : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
                        VRAM_ADDR               : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
                        VRAM_CLOCK              : OUT STD_LOGIC;
                        VRAM_WREN               : OUT STD_LOGIC;
                        VGA_R,
                        VGA_G,
                        VGA_B                   : OUT STD_LOGIC;
                        VGA_HS,
                        VGA_VS                  : OUT STD_LOGIC);
        END COMPONENT;
 
        signal MREQ_n   : std_logic;
        signal IORQ_n   : std_logic;
        signal RD_n             : std_logic;
        signal WR_n             : std_logic;
        signal MWr_n    : std_logic;
        signal Rst_n_s  : std_logic;
        signal Clk_Z80  : std_logic;
        signal DI_CPU   : std_logic_vector(7 downto 0);
        signal DO_CPU   : std_logic_vector(7 downto 0);
        signal A                : std_logic_vector(15 downto 0);
        signal One              : std_logic;
 
        signal D_ROM    : std_logic_vector(7 downto 0);
 
        signal clk25mhz_sig : std_logic;
        signal clk100hz         : std_logic;
        signal clk10hz          : std_logic;
        signal clk1hz           : std_logic;
 
        signal vram_addra_sig           : std_logic_vector(15 downto 0);
        signal vram_addrb_sig           : std_logic_vector(15 downto 0);
        signal vram_addrb_sigv          : std_logic_vector(15 downto 0);
        signal vram_dina_sig                    : std_logic_vector(7 downto 0);
        signal vram_dinb_sig                    : std_logic_vector(7 downto 0);
        signal vram_douta_sig           : std_logic_vector(7 downto 0);
        signal vram_doutb_sig           : std_logic_vector(7 downto 0);
        signal vram_doutb_sigv          : std_logic_vector(7 downto 0);
        signal vram_wea_sig                     : std_logic;
        signal vram_web_sig                     : std_logic;
        signal vram_clka_sig                    : std_logic;
        signal vram_clkb_sig                    : std_logic;
        signal vram_clkb_sigv                   : std_logic;
 
        -- LCD signals
        signal lcd_wea                  : std_logic;
        signal lcd_addra                : std_logic_vector(4 downto 0);
        signal lcd_addrb                : std_logic_vector(4 downto 0);
        signal lcd_dina         : std_logic_vector(7 downto 0);
        signal lcd_doutb                : std_logic_vector(7 downto 0);
 
        -- VGA conversion from 4 bits to 8 bit
        signal VGA_Rs, VGA_Gs, VGA_Bs   : std_logic_vector(3 downto 0);
        signal VGA_HSs, VGA_VSs                 : std_logic;
 
        -- PS/2 Keyboard
        signal ps2_read                                 : std_logic;
        signal ps2_scan_ready                   : std_logic;
        signal ps2_ascii_sig                            : std_logic_vector(7 downto 0);
        signal ps2_ascii_reg1                   : std_logic_vector(7 downto 0);
        signal ps2_ascii_reg                            : std_logic_vector(7 downto 0);
 
begin
 
        Rst_n_s <= not KEY(3);
 
        writevram: process(Clk_Z80)
        begin
                if Clk_Z80'event and Clk_Z80 = '1' then
                        if A >= x"2000" and A <= x"27FF" then
                                vram_addra_sig <= A - x"2000";
                                if Wr_n = '0' and MReq_n = '0' then
                                        vram_dina_sig <= DO_CPU;
                                        vram_wea_sig <= '0';
                                else
                                        vram_wea_sig <= '1';
                                end if;
                        else
                                vram_wea_sig <= '1';
                        end if;
                end if;
        end process;
 
        lcd_process: process(Clk_Z80)
        begin
                if Clk_Z80'event and Clk_Z80 = '1' then
                        if A >= x"3FE0" and A < x"4000" then
                                if MReq_n = '0' and Wr_n = '0' then
                                        lcd_wea <= '0';
                                        lcd_addra <= A - x"3FE0";
                                        lcd_dina <= DO_CPU;
                                else
                                        lcd_wea <= '1';
                                end if;
                        else
                                lcd_wea <= '1';
                  end if;
                end if;
        end process;
 
        DI_CPU <= D_ROM when (Rd_n = '0' and MReq_n = '0' and A < x"2000") else
                        ("0000" & SW) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"20") else
                        ("0000" & KEY) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"30") else
                        ps2_ascii_reg when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"80");
 
        -- Process to latch leds and hex displays
        process(Clk_Z80)
        variable LEDG_sig               : std_logic_vector(7 downto 0);
 
        begin
 
                if Clk_Z80'event and Clk_Z80 = '1' then
                  if IORQ_n = '0' and Wr_n = '0' then
                        -- LEDG
                        if A(7 downto 0) = x"01" then
                                LEDG_sig := DO_CPU;
                        end if;
                  end if;
                end if;
 
                -- Latches the signals
                LEDG <= LEDG_sig;
        end process;
 
        -- the following three processes deals with different clock domain signals
        ps2_process1: process(CLOCK_50)
        begin
                if CLOCK_50'event and CLOCK_50 = '1' then
                        if ps2_read = '1' then
                                if ps2_ascii_sig /= x"FF" then
                                        ps2_read <= '0';
                                        ps2_ascii_reg1 <= "00000000";
                                end if;
                        elsif ps2_scan_ready = '1' then
                                if ps2_ascii_sig = x"FF" then
                                        ps2_read <= '1';
                                else
                                        ps2_ascii_reg1 <= ps2_ascii_sig;
                                end if;
                        end if;
                end if;
        end process;
 
        ps2_process2: process(Clk_Z80)
        begin
                if Clk_Z80'event and Clk_Z80 = '1' then
                        ps2_ascii_reg <= ps2_ascii_reg1;
                end if;
        end process;
 
 
        One <= '1';
        z80_inst: T80s
                port map (
                        M1_n => open,
                        MREQ_n => MReq_n,
                        IORQ_n => IORq_n,
                        RD_n => Rd_n,
                        WR_n => Wr_n,
                        RFSH_n => open,
                        HALT_n => open,
                        WAIT_n => One,
                        INT_n => One,
                        NMI_n => One,
                        RESET_n => Rst_n_s,
                        BUSRQ_n => One,
                        BUSAK_n => open,
                        CLK_n => Clk_Z80,
                        A => A,
                        DI => DI_CPU,
                        DO => DO_CPU
                );
 
        vga80x40_inst: video_80x40 port map (
                        CLOCK_50                        => CLOCK_50,
                        VRAM_DATA               => vram_doutb_sig,
                        VRAM_ADDR               => vram_addrb_sig(12 downto 0),
                        VRAM_CLOCK              => vram_clkb_sig,
                        VRAM_WREN               => vram_web_sig,
                        VGA_R                           => VGA_R,
                        VGA_G                           => VGA_G,
                        VGA_B                           => VGA_B,
                        VGA_HS                  => VGA_HS,
                        VGA_VS                  => VGA_VS
        );
 
        vram_inst: vram port map (
                clka            => Clk_Z80,
                clkb            => vram_clkb_sig,
      wea       => vram_wea_sig,
      addra             => vram_addra_sig(10 downto 0),
      addrb             => vram_addrb_sig(10 downto 0),
      dina      => vram_dina_sig,
                doutb           => vram_doutb_sig
        );
 
        rom_inst: rom
                port map (
                        clk => Clk_Z80,
                        addr    => A(12 downto 0),
                        dout    => D_ROM
                );
 
        ps2_kbd_inst : ps2kbd PORT MAP (
                keyboard_clk    => PS2_CLK,
                keyboard_data   => PS2_DAT,
                clock                   => CLOCK_50,
                clkdelay                => clk100hz,
                reset                   => Rst_n_s,
                read                    => ps2_read,
                scan_ready              => ps2_scan_ready,
                ps2_ascii_code  => ps2_ascii_sig
        );
 
 
        process (CLOCK_50)
   begin
                if CLOCK_50'event and CLOCK_50 = '1' then
        clk25mhz_sig <= not clk25mhz_sig;
                end if;
   end process;
 
                clock_z80_inst : Clock_357Mhz
                port map (
                        clock_50Mhz             => CLOCK_50,
                        clock_357Mhz    => Clk_Z80
        );
 
   clkdiv_inst: clk_div
                port map (
                clock_25Mhz             => clk25mhz_sig,
                clock_1MHz              => open,
                clock_100KHz    => open,
                clock_10KHz             => open,
                clock_1KHz              => open,
                clock_100Hz             => clk100hz,
                clock_10Hz              => clk10hz,
                clock_1Hz               => clk1hz
        );
 
        lcd_inst: lcd
        port map (
                clk                     => CLOCK_50,
                reset                   => not Rst_n_s,
                SF_D                    => SF_D,
                LCD_E                   => LCD_E,
                LCD_RS          => LCD_RS,
                LCD_RW          => LCD_RW,
                SF_CE0          => SF_CE0,
                lcd_addr                => lcd_addrb,
                lcd_char                => lcd_doutb
        );
 
        lcdvram_inst : lcdvram
                port map (
                        addra => lcd_addra,
                        addrb => lcd_addrb,
                        clka => Clk_Z80,
                        clkb => CLOCK_50,
                        dina => lcd_dina,
                        doutb => lcd_doutb,
                        wea => lcd_wea
                );
 
end;

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Subversion Repositories z80soc

[/] [z80soc/] [branches/] [RonivonCosta/] [S3E/] [top_s3e.vhd] - Blame information for rev 11

Line No.	Rev	Author	Line
1	11	rrred	`-------------------------------------------------------------------------------------------------`
2			`-- Z80_Soc (Z80 System on Chip)`
3			`--`
4			`-- Version 0.5 Beta`
5			`--`
6			`-- Developer: Ronivon Candido Costa`
7			`-- Release Date: 2008 / 04 / 16`
8			`--`
9			`-- Based on the T80 core: http://www.opencores.org/projects.cgi/web/t80`
10			`-- This version developed and tested on: Altera DE1 Development Board`
11			`--`
12			`-- Peripherals configured (Using Ports):`
13			`--`
14			`-- 08 KB Internal ROM Read (0x0000h - 0x1FFFh)`
15			`-- 08 KB INTERNAL VRAM Write (0x2000h - 0x3FFFh)`
16			`-- 48 KB External SRAM Read/Write (0x4000h - 0xFFFFh)`
17			`-- 08 Green Leds Out (Port 0x01h)`
18			`-- 08 Red Leds Out (Port 0x02h)`
19			`-- 04 Seven Seg displays Out (Ports 0x10h and 0x11h)`
20			`-- 36 Pins GPIO0 In/Out (Ports 0xA0h, 0xA1h, 0xA2h, 0xA3h, 0xA4h, 0xC0h)`
21			`-- 36 Pins GPIO1 In/Out (Ports 0xB0h, 0xB1h, 0xB2h, 0xB3h, 0xB4h, 0xC1h)`
22			`-- 08 Switches In (Port 0x20h)`
23			`-- 04 Push buttons In (Port 0x30h)`
24			`-- PS/2 keyboard In (Port 0x80h)`
25			`-- Video Out (VGA) Out (0x2000h - 0x24B0)`
26			`--`
27			`--`
28			`-- Revision history:`
29			`--`
30			`-- 2008/04(21 - Ported to Spartan 3E`
31			`--`
32			`-- 2008/04/17 - Added Video support for 80x40 mode`
33			`-- 2008/04/16 - Release Version 0.5-DE1-Beta`
34			`--`
35			`-- TO-DO:`
36			`-- - Monitor program to introduce Z80 Assmebly codes and run`
37			`-- - Serial communication, to download assembly code from PC`
38			`-- - Add hardware support for 80x40 Video out`
39			`-- - SD/MMC card interface to read/store data and programs`
40			`-------------------------------------------------------------------------------------------------`
41
42			`library IEEE;`
43			`use IEEE.std_logic_1164.all;`
44			`use IEEE.std_logic_arith.all;`
45			`use IEEE.std_logic_unsigned.all;`
46
47			`entity Z80SOC_TOP is`
48			`generic (`
49			`swcount : integer := 4;`
50			`keycount : integer := 4;`
51			`ledrcount : integer := 10;`
52			`ledgcount : integer := 8;`
53			`sramdepth : integer := 16;`
54			`dramdepth : integer := 13;`
55			`framdepth : integer := 25;`
56			`vgadepth : integer := 1);`
57			`port(`
58			`-- Clocks`
59			`CLOCK_50 : in std_logic; -- 50 MHz`
60
61			`-- Buttons and switches`
62			`KEY : in std_logic_vector(keycount - 1 downto 0); -- Push buttons`
63			`SW : in std_logic_vector(swcount-1 downto 0); -- Switches`
64
65			`-- LED displays`
66			`LEDG : out std_logic_vector(ledgcount-1 downto 0); -- Green LEDs`
67
68			`-- RS-232 interface`
69			`-- UART_TXD : out std_logic; -- UART transmitter`
70			`-- UART_RXD : in std_logic; -- UART receiver`
71
72			`-- PS/2 port`
73			`PS2_DAT, -- Data`
74			`PS2_CLK : inout std_logic; -- Clock`
75
76			`-- VGA output`
77			`VGA_HS, -- H_SYNC`
78			`VGA_VS : out std_logic; -- SYNC`
79			`VGA_R, -- Red[3:0]`
80			`VGA_G, -- Green[3:0]`
81			`VGA_B : out std_logic; -- Blue[3:0]`
82			`SF_D : out std_logic_vector(3 downto 0);`
83			`LCD_E, LCD_RS, LCD_RW, SF_CE0 : out std_logic`
84			`);`
85			`end Z80SOC_TOP;`
86
87			`architecture rtl of Z80SOC_TOP is`
88
89			`component clk_div`
90			`PORT`
91			`(`
92			`clock_25Mhz : IN STD_LOGIC;`
93			`clock_1MHz : OUT STD_LOGIC;`
94			`clock_100KHz : OUT STD_LOGIC;`
95			`clock_10KHz : OUT STD_LOGIC;`
96			`clock_1KHz : OUT STD_LOGIC;`
97			`clock_100Hz : OUT STD_LOGIC;`
98			`clock_10Hz : OUT STD_LOGIC;`
99			`clock_1Hz : OUT STD_LOGIC);`
100			`end component;`
101
102			`component T80s`
103			`generic(`
104			`Mode : integer := 0);`
105			`port (`
106			`RESET_n : in std_logic;`
107			`CLK_n : in std_logic;`
108			`WAIT_n : in std_logic;`
109			`INT_n : in std_logic;`
110			`NMI_n : in std_logic;`
111			`BUSRQ_n : in std_logic;`
112			`M1_n : out std_logic;`
113			`MREQ_n : out std_logic;`
114			`IORQ_n : out std_logic;`
115			`RD_n : out std_logic;`
116			`WR_n : out std_logic;`
117			`RFSH_n : out std_logic;`
118			`HALT_n : out std_logic;`
119			`BUSAK_n : out std_logic;`
120			`A : out std_logic_vector(15 downto 0);`
121			`DI : in std_logic_vector(7 downto 0);`
122			`DO : out std_logic_vector(7 downto 0));`
123			`end component;`
124
125			`component lcd`
126			`port(`
127			`clk, reset : in std_logic;`
128			`SF_D : out std_logic_vector(3 downto 0);`
129			`LCD_E, LCD_RS, LCD_RW, SF_CE0 : out std_logic;`
130			`lcd_addr : out std_logic_vector(4 downto 0);`
131			`lcd_char : in std_logic_vector(7 downto 0));`
132			`end component;`
133
134			`component lcdvram`
135			`port (`
136			`addra: IN std_logic_VECTOR(4 downto 0);`
137			`addrb: IN std_logic_VECTOR(4 downto 0);`
138			`clka: IN std_logic;`
139			`clkb: IN std_logic;`
140			`dina: IN std_logic_VECTOR(7 downto 0);`
141			`doutb: OUT std_logic_VECTOR(7 downto 0);`
142			`wea: IN std_logic);`
143			`end component;`
144
145			`component rom`
146			`port (`
147			`clk : in std_logic;`
148			`addr : in std_logic_vector(12 downto 0);`
149			`dout : out std_logic_vector(7 downto 0));`
150			`end component;`
151
152			`component Clock_357Mhz`
153			`PORT (`
154			`clock_50Mhz : IN STD_LOGIC;`
155			`clock_357Mhz : OUT STD_LOGIC);`
156			`end component;`
157
158			`component ps2kbd`
159			`PORT (`
160			`keyboard_clk : inout std_logic;`
161			`keyboard_data : inout std_logic;`
162			`clock : in std_logic;`
163			`clkdelay : in std_logic;`
164			`reset : in std_logic;`
165			`read : in std_logic;`
166			`scan_ready : out std_logic;`
167			`ps2_ascii_code : out std_logic_vector(7 downto 0));`
168			`end component;`
169
170			`component vram`
171			`port (`
172			`addra: IN std_logic_VECTOR(10 downto 0);`
173			`addrb: IN std_logic_VECTOR(10 downto 0);`
174			`clka: IN std_logic;`
175			`clkb: IN std_logic;`
176			`dina: IN std_logic_VECTOR(7 downto 0);`
177			`doutb: OUT std_logic_VECTOR(7 downto 0);`
178			`wea: IN std_logic);`
179			`end component;`
180
181			`COMPONENT video_80x40`
182			`PORT( CLOCK_50 : IN STD_LOGIC;`
183			`VRAM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
184			`VRAM_ADDR : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);`
185			`VRAM_CLOCK : OUT STD_LOGIC;`
186			`VRAM_WREN : OUT STD_LOGIC;`
187			`VGA_R,`
188			`VGA_G,`
189			`VGA_B : OUT STD_LOGIC;`
190			`VGA_HS,`
191			`VGA_VS : OUT STD_LOGIC);`
192			`END COMPONENT;`
193
194			`signal MREQ_n : std_logic;`
195			`signal IORQ_n : std_logic;`
196			`signal RD_n : std_logic;`
197			`signal WR_n : std_logic;`
198			`signal MWr_n : std_logic;`
199			`signal Rst_n_s : std_logic;`
200			`signal Clk_Z80 : std_logic;`
201			`signal DI_CPU : std_logic_vector(7 downto 0);`
202			`signal DO_CPU : std_logic_vector(7 downto 0);`
203			`signal A : std_logic_vector(15 downto 0);`
204			`signal One : std_logic;`
205
206			`signal D_ROM : std_logic_vector(7 downto 0);`
207
208			`signal clk25mhz_sig : std_logic;`
209			`signal clk100hz : std_logic;`
210			`signal clk10hz : std_logic;`
211			`signal clk1hz : std_logic;`
212
213			`signal vram_addra_sig : std_logic_vector(15 downto 0);`
214			`signal vram_addrb_sig : std_logic_vector(15 downto 0);`
215			`signal vram_addrb_sigv : std_logic_vector(15 downto 0);`
216			`signal vram_dina_sig : std_logic_vector(7 downto 0);`
217			`signal vram_dinb_sig : std_logic_vector(7 downto 0);`
218			`signal vram_douta_sig : std_logic_vector(7 downto 0);`
219			`signal vram_doutb_sig : std_logic_vector(7 downto 0);`
220			`signal vram_doutb_sigv : std_logic_vector(7 downto 0);`
221			`signal vram_wea_sig : std_logic;`
222			`signal vram_web_sig : std_logic;`
223			`signal vram_clka_sig : std_logic;`
224			`signal vram_clkb_sig : std_logic;`
225			`signal vram_clkb_sigv : std_logic;`
226
227			`-- LCD signals`
228			`signal lcd_wea : std_logic;`
229			`signal lcd_addra : std_logic_vector(4 downto 0);`
230			`signal lcd_addrb : std_logic_vector(4 downto 0);`
231			`signal lcd_dina : std_logic_vector(7 downto 0);`
232			`signal lcd_doutb : std_logic_vector(7 downto 0);`
233
234			`-- VGA conversion from 4 bits to 8 bit`
235			`signal VGA_Rs, VGA_Gs, VGA_Bs : std_logic_vector(3 downto 0);`
236			`signal VGA_HSs, VGA_VSs : std_logic;`
237
238			`-- PS/2 Keyboard`
239			`signal ps2_read : std_logic;`
240			`signal ps2_scan_ready : std_logic;`
241			`signal ps2_ascii_sig : std_logic_vector(7 downto 0);`
242			`signal ps2_ascii_reg1 : std_logic_vector(7 downto 0);`
243			`signal ps2_ascii_reg : std_logic_vector(7 downto 0);`
244
245			`begin`
246
247			`Rst_n_s <= not KEY(3);`
248
249			`writevram: process(Clk_Z80)`
250			`begin`
251			`if Clk_Z80'event and Clk_Z80 = '1' then`
252			`if A >= x"2000" and A <= x"27FF" then`
253			`vram_addra_sig <= A - x"2000";`
254			`if Wr_n = '0' and MReq_n = '0' then`
255			`vram_dina_sig <= DO_CPU;`
256			`vram_wea_sig <= '0';`
257			`else`
258			`vram_wea_sig <= '1';`
259			`end if;`
260			`else`
261			`vram_wea_sig <= '1';`
262			`end if;`
263			`end if;`
264			`end process;`
265
266			`lcd_process: process(Clk_Z80)`
267			`begin`
268			`if Clk_Z80'event and Clk_Z80 = '1' then`
269			`if A >= x"3FE0" and A < x"4000" then`
270			`if MReq_n = '0' and Wr_n = '0' then`
271			`lcd_wea <= '0';`
272			`lcd_addra <= A - x"3FE0";`
273			`lcd_dina <= DO_CPU;`
274			`else`
275			`lcd_wea <= '1';`
276			`end if;`
277			`else`
278			`lcd_wea <= '1';`
279			`end if;`
280			`end if;`
281			`end process;`
282
283			`DI_CPU <= D_ROM when (Rd_n = '0' and MReq_n = '0' and A < x"2000") else`
284			`("0000" & SW) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"20") else`
285			`("0000" & KEY) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"30") else`
286			`ps2_ascii_reg when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"80");`
287
288			`-- Process to latch leds and hex displays`
289			`process(Clk_Z80)`
290			`variable LEDG_sig : std_logic_vector(7 downto 0);`
291
292			`begin`
293
294			`if Clk_Z80'event and Clk_Z80 = '1' then`
295			`if IORQ_n = '0' and Wr_n = '0' then`
296			`-- LEDG`
297			`if A(7 downto 0) = x"01" then`
298			`LEDG_sig := DO_CPU;`
299			`end if;`
300			`end if;`
301			`end if;`
302
303			`-- Latches the signals`
304			`LEDG <= LEDG_sig;`
305			`end process;`
306
307			`-- the following three processes deals with different clock domain signals`
308			`ps2_process1: process(CLOCK_50)`
309			`begin`
310			`if CLOCK_50'event and CLOCK_50 = '1' then`
311			`if ps2_read = '1' then`
312			`if ps2_ascii_sig /= x"FF" then`
313			`ps2_read <= '0';`
314			`ps2_ascii_reg1 <= "00000000";`
315			`end if;`
316			`elsif ps2_scan_ready = '1' then`
317			`if ps2_ascii_sig = x"FF" then`
318			`ps2_read <= '1';`
319			`else`
320			`ps2_ascii_reg1 <= ps2_ascii_sig;`
321			`end if;`
322			`end if;`
323			`end if;`
324			`end process;`
325
326			`ps2_process2: process(Clk_Z80)`
327			`begin`
328			`if Clk_Z80'event and Clk_Z80 = '1' then`
329			`ps2_ascii_reg <= ps2_ascii_reg1;`
330			`end if;`
331			`end process;`
332
333
334			`One <= '1';`
335			`z80_inst: T80s`
336			`port map (`
337			`M1_n => open,`
338			`MREQ_n => MReq_n,`
339			`IORQ_n => IORq_n,`
340			`RD_n => Rd_n,`
341			`WR_n => Wr_n,`
342			`RFSH_n => open,`
343			`HALT_n => open,`
344			`WAIT_n => One,`
345			`INT_n => One,`
346			`NMI_n => One,`
347			`RESET_n => Rst_n_s,`
348			`BUSRQ_n => One,`
349			`BUSAK_n => open,`
350			`CLK_n => Clk_Z80,`
351			`A => A,`
352			`DI => DI_CPU,`
353			`DO => DO_CPU`
354			`);`
355
356			`vga80x40_inst: video_80x40 port map (`
357			`CLOCK_50 => CLOCK_50,`
358			`VRAM_DATA => vram_doutb_sig,`
359			`VRAM_ADDR => vram_addrb_sig(12 downto 0),`
360			`VRAM_CLOCK => vram_clkb_sig,`
361			`VRAM_WREN => vram_web_sig,`
362			`VGA_R => VGA_R,`
363			`VGA_G => VGA_G,`
364			`VGA_B => VGA_B,`
365			`VGA_HS => VGA_HS,`
366			`VGA_VS => VGA_VS`
367			`);`
368
369			`vram_inst: vram port map (`
370			`clka => Clk_Z80,`
371			`clkb => vram_clkb_sig,`
372			`wea => vram_wea_sig,`
373			`addra => vram_addra_sig(10 downto 0),`
374			`addrb => vram_addrb_sig(10 downto 0),`
375			`dina => vram_dina_sig,`
376			`doutb => vram_doutb_sig`
377			`);`
378
379			`rom_inst: rom`
380			`port map (`
381			`clk => Clk_Z80,`
382			`addr => A(12 downto 0),`
383			`dout => D_ROM`
384			`);`
385
386			`ps2_kbd_inst : ps2kbd PORT MAP (`
387			`keyboard_clk => PS2_CLK,`
388			`keyboard_data => PS2_DAT,`
389			`clock => CLOCK_50,`
390			`clkdelay => clk100hz,`
391			`reset => Rst_n_s,`
392			`read => ps2_read,`
393			`scan_ready => ps2_scan_ready,`
394			`ps2_ascii_code => ps2_ascii_sig`
395			`);`
396
397
398			`process (CLOCK_50)`
399			`begin`
400			`if CLOCK_50'event and CLOCK_50 = '1' then`
401			`clk25mhz_sig <= not clk25mhz_sig;`
402			`end if;`
403			`end process;`
404
405			`clock_z80_inst : Clock_357Mhz`
406			`port map (`
407			`clock_50Mhz => CLOCK_50,`
408			`clock_357Mhz => Clk_Z80`
409			`);`
410
411			`clkdiv_inst: clk_div`
412			`port map (`
413			`clock_25Mhz => clk25mhz_sig,`
414			`clock_1MHz => open,`
415			`clock_100KHz => open,`
416			`clock_10KHz => open,`
417			`clock_1KHz => open,`
418			`clock_100Hz => clk100hz,`
419			`clock_10Hz => clk10hz,`
420			`clock_1Hz => clk1hz`
421			`);`
422
423			`lcd_inst: lcd`
424			`port map (`
425			`clk => CLOCK_50,`
426			`reset => not Rst_n_s,`
427			`SF_D => SF_D,`
428			`LCD_E => LCD_E,`
429			`LCD_RS => LCD_RS,`
430			`LCD_RW => LCD_RW,`
431			`SF_CE0 => SF_CE0,`
432			`lcd_addr => lcd_addrb,`
433			`lcd_char => lcd_doutb`
434			`);`
435
436			`lcdvram_inst : lcdvram`
437			`port map (`
438			`addra => lcd_addra,`
439			`addrb => lcd_addrb,`
440			`clka => Clk_Z80,`
441			`clkb => CLOCK_50,`
442			`dina => lcd_dina,`
443			`doutb => lcd_doutb,`
444			`wea => lcd_wea`
445			`);`
446
447			`end;`