1 |
2 |
rrred |
-------------------------------------------------------------------------------------------------
|
2 |
|
|
-- Z80_Soc (Z80 System on Chip)
|
3 |
|
|
--
|
4 |
|
|
-- Version 0.5 Beta
|
5 |
|
|
--
|
6 |
|
|
-- Developer: Ronivon Candido Costa
|
7 |
|
|
-- Release Date: 2008 / 04 / 16
|
8 |
|
|
--
|
9 |
|
|
-- Based on the T80 core: http://www.opencores.org/projects.cgi/web/t80
|
10 |
|
|
-- This version developed and tested on: Altera DE1 Development Board
|
11 |
|
|
--
|
12 |
|
|
-- Peripherals configured (Using Ports):
|
13 |
|
|
--
|
14 |
|
|
-- 08 KB Internal ROM Read (0x0000h - 0x1FFFh)
|
15 |
|
|
-- 08 KB INTERNAL VRAM Write (0x2000h - 0x3FFFh)
|
16 |
|
|
-- 48 KB External SRAM Read/Write (0x4000h - 0xFFFFh)
|
17 |
|
|
-- 08 Green Leds Out (Port 0x01h)
|
18 |
|
|
-- 08 Red Leds Out (Port 0x02h)
|
19 |
|
|
-- 04 Seven Seg displays Out (Ports 0x10h and 0x11h)
|
20 |
|
|
-- 36 Pins GPIO0 In/Out (Ports 0xA0h, 0xA1h, 0xA2h, 0xA3h, 0xA4h, 0xC0h)
|
21 |
|
|
-- 36 Pins GPIO1 In/Out (Ports 0xB0h, 0xB1h, 0xB2h, 0xB3h, 0xB4h, 0xC1h)
|
22 |
|
|
-- 08 Switches In (Port 0x20h)
|
23 |
|
|
-- 04 Push buttons In (Port 0x30h)
|
24 |
|
|
-- PS/2 keyboard In (Port 0x80h)
|
25 |
|
|
-- Video Out 40x30 (VGA) Out (0x2000h - 0x24B0)
|
26 |
|
|
--
|
27 |
|
|
-- TO-DO:
|
28 |
|
|
-- - Monitor program to introduce Z80 Assmebly codes and run
|
29 |
|
|
-- - Serial communication, to download assembly code from PC
|
30 |
|
|
-- - Add hardware support for 80x40 Video out
|
31 |
|
|
-- - SD/MMC card interface to read/store data and programs
|
32 |
|
|
-------------------------------------------------------------------------------------------------
|
33 |
|
|
|
34 |
|
|
library IEEE;
|
35 |
|
|
use IEEE.std_logic_1164.all;
|
36 |
|
|
use IEEE.std_logic_arith.all;
|
37 |
|
|
use IEEE.std_logic_unsigned.all;
|
38 |
|
|
|
39 |
|
|
entity TOP_DE1 is
|
40 |
|
|
port(
|
41 |
|
|
|
42 |
|
|
-- Clocks
|
43 |
|
|
CLOCK_27, -- 27 MHz
|
44 |
|
|
CLOCK_50, -- 50 MHz
|
45 |
|
|
EXT_CLOCK : in std_logic; -- External Clock
|
46 |
|
|
|
47 |
|
|
-- Buttons and switches
|
48 |
|
|
KEY : in std_logic_vector(3 downto 0); -- Push buttons
|
49 |
|
|
SW : in std_logic_vector(9 downto 0); -- Switches
|
50 |
|
|
|
51 |
|
|
-- LED displays
|
52 |
|
|
HEX0, HEX1, HEX2, HEX3 -- 7-segment displays
|
53 |
|
|
: out std_logic_vector(6 downto 0);
|
54 |
|
|
LEDG : out std_logic_vector(7 downto 0); -- Green LEDs
|
55 |
|
|
LEDR : out std_logic_vector(9 downto 0); -- Red LEDs
|
56 |
|
|
|
57 |
|
|
-- RS-232 interface
|
58 |
|
|
UART_TXD : out std_logic; -- UART transmitter
|
59 |
|
|
UART_RXD : in std_logic; -- UART receiver
|
60 |
|
|
|
61 |
|
|
-- IRDA interface
|
62 |
|
|
|
63 |
|
|
-- IRDA_TXD : out std_logic; -- IRDA Transmitter
|
64 |
|
|
IRDA_RXD : in std_logic; -- IRDA Receiver
|
65 |
|
|
|
66 |
|
|
-- SDRAM
|
67 |
|
|
DRAM_DQ : inout std_logic_vector(15 downto 0); -- Data Bus
|
68 |
|
|
DRAM_ADDR : out std_logic_vector(11 downto 0); -- Address Bus
|
69 |
|
|
DRAM_LDQM, -- Low-byte Data Mask
|
70 |
|
|
DRAM_UDQM, -- High-byte Data Mask
|
71 |
|
|
DRAM_WE_N, -- Write Enable
|
72 |
|
|
DRAM_CAS_N, -- Column Address Strobe
|
73 |
|
|
DRAM_RAS_N, -- Row Address Strobe
|
74 |
|
|
DRAM_CS_N, -- Chip Select
|
75 |
|
|
DRAM_BA_0, -- Bank Address 0
|
76 |
|
|
DRAM_BA_1, -- Bank Address 0
|
77 |
|
|
DRAM_CLK, -- Clock
|
78 |
|
|
DRAM_CKE : out std_logic; -- Clock Enable
|
79 |
|
|
|
80 |
|
|
-- FLASH
|
81 |
|
|
FL_DQ : inout std_logic_vector(7 downto 0); -- Data bus
|
82 |
|
|
FL_ADDR : out std_logic_vector(21 downto 0); -- Address bus
|
83 |
|
|
FL_WE_N, -- Write Enable
|
84 |
|
|
FL_RST_N, -- Reset
|
85 |
|
|
FL_OE_N, -- Output Enable
|
86 |
|
|
FL_CE_N : out std_logic; -- Chip Enable
|
87 |
|
|
|
88 |
|
|
-- SRAM
|
89 |
|
|
SRAM_DQ : inout std_logic_vector(15 downto 0); -- Data bus 16 Bits
|
90 |
|
|
SRAM_ADDR : out std_logic_vector(17 downto 0); -- Address bus 18 Bits
|
91 |
|
|
SRAM_UB_N, -- High-byte Data Mask
|
92 |
|
|
SRAM_LB_N, -- Low-byte Data Mask
|
93 |
|
|
SRAM_WE_N, -- Write Enable
|
94 |
|
|
SRAM_CE_N, -- Chip Enable
|
95 |
|
|
SRAM_OE_N : out std_logic; -- Output Enable
|
96 |
|
|
|
97 |
|
|
-- SD card interface
|
98 |
|
|
SD_DAT : in std_logic; -- SD Card Data SD pin 7 "DAT 0/DataOut"
|
99 |
|
|
SD_DAT3 : out std_logic; -- SD Card Data 3 SD pin 1 "DAT 3/nCS"
|
100 |
|
|
SD_CMD : out std_logic; -- SD Card Command SD pin 2 "CMD/DataIn"
|
101 |
|
|
SD_CLK : out std_logic; -- SD Card Clock SD pin 5 "CLK"
|
102 |
|
|
|
103 |
|
|
-- USB JTAG link
|
104 |
|
|
TDI, -- CPLD -> FPGA (data in)
|
105 |
|
|
TCK, -- CPLD -> FPGA (clk)
|
106 |
|
|
TCS : in std_logic; -- CPLD -> FPGA (CS)
|
107 |
|
|
TDO : out std_logic; -- FPGA -> CPLD (data out)
|
108 |
|
|
|
109 |
|
|
-- I2C bus
|
110 |
|
|
I2C_SDAT : inout std_logic; -- I2C Data
|
111 |
|
|
I2C_SCLK : out std_logic; -- I2C Clock
|
112 |
|
|
|
113 |
|
|
-- PS/2 port
|
114 |
|
|
PS2_DAT, -- Data
|
115 |
|
|
PS2_CLK : inout std_logic; -- Clock
|
116 |
|
|
|
117 |
|
|
-- VGA output
|
118 |
|
|
VGA_HS, -- H_SYNC
|
119 |
|
|
VGA_VS : out std_logic; -- SYNC
|
120 |
|
|
VGA_R, -- Red[3:0]
|
121 |
|
|
VGA_G, -- Green[3:0]
|
122 |
|
|
VGA_B : out std_logic_vector(3 downto 0); -- Blue[3:0]
|
123 |
|
|
|
124 |
|
|
-- Audio CODEC
|
125 |
|
|
AUD_ADCLRCK : inout std_logic; -- ADC LR Clock
|
126 |
|
|
AUD_ADCDAT : in std_logic; -- ADC Data
|
127 |
|
|
AUD_DACLRCK : inout std_logic; -- DAC LR Clock
|
128 |
|
|
AUD_DACDAT : out std_logic; -- DAC Data
|
129 |
|
|
AUD_BCLK : inout std_logic; -- Bit-Stream Clock
|
130 |
|
|
AUD_XCK : out std_logic; -- Chip Clock
|
131 |
|
|
|
132 |
|
|
-- General-purpose I/O
|
133 |
|
|
GPIO_0, -- GPIO Connection 0
|
134 |
|
|
GPIO_1 : inout std_logic_vector(35 downto 0) -- GPIO Connection 1
|
135 |
|
|
);
|
136 |
|
|
end TOP_DE1;
|
137 |
|
|
|
138 |
|
|
architecture rtl of TOP_DE1 is
|
139 |
|
|
|
140 |
|
|
component T80s
|
141 |
|
|
generic(
|
142 |
|
|
Mode : integer := 0);
|
143 |
|
|
port (
|
144 |
|
|
RESET_n : in std_logic;
|
145 |
|
|
CLK_n : in std_logic;
|
146 |
|
|
WAIT_n : in std_logic;
|
147 |
|
|
INT_n : in std_logic;
|
148 |
|
|
NMI_n : in std_logic;
|
149 |
|
|
BUSRQ_n : in std_logic;
|
150 |
|
|
M1_n : out std_logic;
|
151 |
|
|
MREQ_n : out std_logic;
|
152 |
|
|
IORQ_n : out std_logic;
|
153 |
|
|
RD_n : out std_logic;
|
154 |
|
|
WR_n : out std_logic;
|
155 |
|
|
RFSH_n : out std_logic;
|
156 |
|
|
HALT_n : out std_logic;
|
157 |
|
|
BUSAK_n : out std_logic;
|
158 |
|
|
A : out std_logic_vector(15 downto 0);
|
159 |
|
|
DI : in std_logic_vector(7 downto 0);
|
160 |
|
|
DO : out std_logic_vector(7 downto 0));
|
161 |
|
|
end component;
|
162 |
|
|
|
163 |
|
|
component rom
|
164 |
|
|
port (
|
165 |
|
|
Clk : in std_logic;
|
166 |
|
|
A : in std_logic_vector(15 downto 0);
|
167 |
|
|
D : out std_logic_vector(7 downto 0));
|
168 |
|
|
end component;
|
169 |
|
|
|
170 |
|
|
component Clock_357Mhz
|
171 |
|
|
PORT (
|
172 |
|
|
clock_50Mhz : IN STD_LOGIC;
|
173 |
|
|
clock_357Mhz : OUT STD_LOGIC);
|
174 |
|
|
end component;
|
175 |
|
|
|
176 |
|
|
component clk_div
|
177 |
|
|
PORT
|
178 |
|
|
(
|
179 |
|
|
clock_25Mhz : IN STD_LOGIC;
|
180 |
|
|
clock_1MHz : OUT STD_LOGIC;
|
181 |
|
|
clock_100KHz : OUT STD_LOGIC;
|
182 |
|
|
clock_10KHz : OUT STD_LOGIC;
|
183 |
|
|
clock_1KHz : OUT STD_LOGIC;
|
184 |
|
|
clock_100Hz : OUT STD_LOGIC;
|
185 |
|
|
clock_10Hz : OUT STD_LOGIC;
|
186 |
|
|
clock_1Hz : OUT STD_LOGIC);
|
187 |
|
|
end component;
|
188 |
|
|
|
189 |
|
|
component decoder_7seg
|
190 |
|
|
port (
|
191 |
|
|
NUMBER : in std_logic_vector(3 downto 0);
|
192 |
|
|
HEX_DISP : out std_logic_vector(6 downto 0));
|
193 |
|
|
end component;
|
194 |
|
|
|
195 |
|
|
signal MREQ_n : std_logic;
|
196 |
|
|
signal IORQ_n : std_logic;
|
197 |
|
|
signal RD_n : std_logic;
|
198 |
|
|
signal WR_n : std_logic;
|
199 |
|
|
signal MWr_n : std_logic;
|
200 |
|
|
signal Rst_n_s : std_logic;
|
201 |
|
|
signal Clk_Z80 : std_logic;
|
202 |
|
|
signal DI_CPU : std_logic_vector(7 downto 0);
|
203 |
|
|
signal DO_CPU : std_logic_vector(7 downto 0);
|
204 |
|
|
signal A : std_logic_vector(15 downto 0);
|
205 |
|
|
signal One : std_logic;
|
206 |
|
|
|
207 |
|
|
signal D_ROM : std_logic_vector(7 downto 0);
|
208 |
|
|
|
209 |
|
|
signal clk25mhz_sig : std_logic;
|
210 |
9 |
rrred |
signal clk25mhz : std_logic;
|
211 |
|
|
signal clk1hz : std_logic;
|
212 |
|
|
signal clk10hz : std_logic;
|
213 |
|
|
signal clk100hz : std_logic;
|
214 |
2 |
rrred |
|
215 |
|
|
signal HEX_DISP0 : std_logic_vector(6 downto 0);
|
216 |
|
|
signal HEX_DISP1 : std_logic_vector(6 downto 0);
|
217 |
|
|
signal HEX_DISP2 : std_logic_vector(6 downto 0);
|
218 |
|
|
signal HEX_DISP3 : std_logic_vector(6 downto 0);
|
219 |
|
|
|
220 |
|
|
signal NUMBER0 : std_logic_vector(3 downto 0);
|
221 |
|
|
signal NUMBER1 : std_logic_vector(3 downto 0);
|
222 |
|
|
signal NUMBER2 : std_logic_vector(3 downto 0);
|
223 |
|
|
signal NUMBER3 : std_logic_vector(3 downto 0);
|
224 |
|
|
|
225 |
|
|
signal GPIO_0_buf_in : std_logic_vector(35 downto 0);
|
226 |
|
|
signal GPIO_1_buf_in : std_logic_vector(35 downto 0);
|
227 |
|
|
|
228 |
|
|
signal vram_rdaddress_sig : std_logic_vector(12 downto 0);
|
229 |
|
|
signal vram_wraddress_sig : std_logic_vector(15 downto 0);
|
230 |
|
|
signal vram_data_sig : std_logic_vector(7 downto 0);
|
231 |
|
|
signal vram_q_sig : std_logic_vector(7 downto 0);
|
232 |
|
|
signal vram_q_reg : std_logic_vector(7 downto 0);
|
233 |
|
|
signal vram_wren_sig : std_logic;
|
234 |
|
|
signal vram_rden_sig : std_logic;
|
235 |
|
|
signal vram_rdcycle_count : std_logic_vector(3 downto 0);
|
236 |
|
|
signal vram_wrcycle_count : std_logic_vector(3 downto 0);
|
237 |
|
|
signal VRAM_CLOCK : std_logic;
|
238 |
|
|
|
239 |
|
|
-- PS/2 Keyboard
|
240 |
|
|
signal ps2_read : std_logic;
|
241 |
|
|
signal ps2_scan_ready : std_logic;
|
242 |
|
|
signal ps2_ascii_sig : std_logic_vector(7 downto 0);
|
243 |
|
|
signal ps2_ascii_reg1 : std_logic_vector(7 downto 0);
|
244 |
|
|
signal ps2_ascii_reg : std_logic_vector(7 downto 0);
|
245 |
|
|
|
246 |
|
|
begin
|
247 |
|
|
|
248 |
|
|
HEX0 <= HEX_DISP0;
|
249 |
|
|
HEX1 <= HEX_DISP1;
|
250 |
|
|
HEX2 <= HEX_DISP2;
|
251 |
|
|
HEX3 <= HEX_DISP3;
|
252 |
|
|
|
253 |
|
|
SRAM_ADDR(15 downto 0) <= A - x"4000" when (A >= x"4000" and MReq_n = '0');
|
254 |
9 |
rrred |
-- SRAM_ADDR(15 downto 0) <= A - x"4000" when (A >= x"4000" and MReq_n = '0') else A;
|
255 |
|
|
-- this is bad --> SRAM_ADDR(15 downto 0) <= A - x"4000";
|
256 |
2 |
rrred |
SRAM_DQ(15 downto 8) <= (others => 'Z');
|
257 |
|
|
SRAM_ADDR(17 downto 16) <= "00";
|
258 |
|
|
SRAM_UB_N <= '1';
|
259 |
|
|
SRAM_LB_N <= '0';
|
260 |
|
|
SRAM_CE_N <= '0';
|
261 |
|
|
SRAM_WE_N <= Wr_n or MReq_n when A >= x"4000";
|
262 |
|
|
SRAM_OE_N <= Rd_n;
|
263 |
|
|
|
264 |
|
|
-- Write to SRAM (0x4000 - 0xFFFF)
|
265 |
|
|
SRAM_DQ(7 downto 0) <= DO_CPU when (Wr_n = '0' and MReq_n = '0' and A >= x"4000") else (others => 'Z');
|
266 |
|
|
|
267 |
|
|
-- Write into VRAM
|
268 |
9 |
rrred |
-- this is almost ok -->vram_wraddress_sig <= A - x"2000" when (A >= x"2000" and A < x"4000" and MReq_n = '0' and IORQ_n = '1');
|
269 |
2 |
rrred |
vram_wraddress_sig <= A - x"2000" when (A >= x"2000" and A < x"4000" and MReq_n = '0');
|
270 |
9 |
rrred |
-- vram_wraddress_sig <= A - x"2000";
|
271 |
2 |
rrred |
vram_wren_sig <= not Wr_n when (A >= x"2000" and A < x"4000" and IORQ_n = '1');
|
272 |
|
|
vram_data_sig <= DO_CPU when (Wr_n = '0' and MReq_n = '0' and A >= x"2000" and A < x"4000") else (others => 'Z');
|
273 |
9 |
rrred |
-- this is ok --> vram_data_sig <= DO_CPU;
|
274 |
2 |
rrred |
|
275 |
|
|
-- Input to Z80
|
276 |
|
|
DI_CPU <= SRAM_DQ(7 downto 0) when (Rd_n = '0' and MReq_n = '0' and A >= x"4000") else
|
277 |
|
|
-- vram_q_sig when (A >= x"2000" and A < x"4000") else
|
278 |
|
|
D_ROM when (Rd_n = '0' and MReq_n = '0' and A < x"2000") else
|
279 |
|
|
SW(7 downto 0) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"20") else
|
280 |
|
|
("0000" & KEY) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"30") else
|
281 |
|
|
GPIO_0(7 downto 0) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"A0") else
|
282 |
|
|
GPIO_0(15 downto 8) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"A1") else
|
283 |
|
|
GPIO_0(23 downto 16) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"A2") else
|
284 |
|
|
GPIO_0(31 downto 24) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"A3") else
|
285 |
|
|
("0000" & GPIO_0(35 downto 32)) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"A4") else
|
286 |
|
|
GPIO_1(7 downto 0) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"B0") else
|
287 |
|
|
GPIO_1(15 downto 8) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"B1") else
|
288 |
|
|
GPIO_1(23 downto 16) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"B2") else
|
289 |
|
|
GPIO_1(31 downto 24) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"B3") else
|
290 |
|
|
("0000" & GPIO_1(35 downto 32)) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"B4") else
|
291 |
|
|
ps2_ascii_reg when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"80");
|
292 |
|
|
|
293 |
|
|
-- Process to latch leds and hex displays
|
294 |
|
|
process(Clk_Z80)
|
295 |
|
|
variable NUMBER0_sig : std_logic_vector(3 downto 0);
|
296 |
|
|
variable NUMBER1_sig : std_logic_vector(3 downto 0);
|
297 |
|
|
variable NUMBER2_sig : std_logic_vector(3 downto 0);
|
298 |
|
|
variable NUMBER3_sig : std_logic_vector(3 downto 0);
|
299 |
|
|
variable LEDG_sig : std_logic_vector(7 downto 0);
|
300 |
|
|
variable LEDR_sig : std_logic_vector(9 downto 0);
|
301 |
|
|
|
302 |
|
|
variable GPIO_0_buf_out: std_logic_vector(35 downto 0);
|
303 |
|
|
variable GPIO_1_buf_out: std_logic_vector(35 downto 0);
|
304 |
|
|
|
305 |
|
|
begin
|
306 |
|
|
|
307 |
|
|
if Clk_Z80'event and Clk_Z80 = '1' then
|
308 |
|
|
if IORQ_n = '0' and Wr_n = '0' then
|
309 |
|
|
-- LEDG
|
310 |
|
|
if A(7 downto 0) = x"01" then
|
311 |
|
|
LEDG_sig := DO_CPU;
|
312 |
|
|
-- LEDR
|
313 |
|
|
elsif A(7 downto 0) = x"02" then
|
314 |
|
|
LEDR_sig(7 downto 0) := DO_CPU;
|
315 |
|
|
-- HEX1 and HEX0
|
316 |
|
|
elsif A(7 downto 0) = x"10" then
|
317 |
|
|
NUMBER0_sig := DO_CPU(3 downto 0);
|
318 |
|
|
NUMBER1_sig := DO_CPU(7 downto 4);
|
319 |
|
|
-- HEX3 and HEX2
|
320 |
|
|
elsif A(7 downto 0) = x"11" then
|
321 |
|
|
NUMBER2_sig := DO_CPU(3 downto 0);
|
322 |
|
|
NUMBER3_sig := DO_CPU(7 downto 4);
|
323 |
|
|
-- GPIO_0
|
324 |
|
|
elsif A(7 downto 0) = x"A0" then
|
325 |
|
|
GPIO_0_buf_out(7 downto 0) := DO_CPU;
|
326 |
|
|
elsif A(7 downto 0) = x"A1" then
|
327 |
|
|
GPIO_0_buf_out(15 downto 8) := DO_CPU;
|
328 |
|
|
elsif A(7 downto 0) = x"A2" then
|
329 |
|
|
GPIO_0_buf_out(23 downto 16) := DO_CPU;
|
330 |
|
|
elsif A(7 downto 0) = x"A3" then
|
331 |
|
|
GPIO_0_buf_out(31 downto 24) := DO_CPU;
|
332 |
|
|
elsif A(7 downto 0) = x"A4" then
|
333 |
|
|
GPIO_0_buf_out(35 downto 32) := DO_CPU(3 downto 0);
|
334 |
|
|
-- GPIO_1
|
335 |
|
|
elsif A(7 downto 0) = x"B0" then
|
336 |
|
|
GPIO_1_buf_out(7 downto 0) := DO_CPU;
|
337 |
|
|
elsif A(7 downto 0) = x"B1" then
|
338 |
|
|
GPIO_1_buf_out(15 downto 8) := DO_CPU;
|
339 |
|
|
elsif A(7 downto 0) = x"B2" then
|
340 |
|
|
GPIO_1_buf_out(23 downto 16) := DO_CPU;
|
341 |
|
|
elsif A(7 downto 0) = x"B3" then
|
342 |
|
|
GPIO_1_buf_out(31 downto 24) := DO_CPU;
|
343 |
|
|
elsif A(7 downto 0) = x"B4" then
|
344 |
|
|
GPIO_1_buf_out(35 downto 32) := DO_CPU(3 downto 0);
|
345 |
|
|
elsif A(7 downto 0) = x"C0" then
|
346 |
|
|
GPIO_0 <= GPIO_0_buf_out;
|
347 |
|
|
elsif A(7 downto 0) = x"C1" then
|
348 |
|
|
GPIO_1 <= GPIO_1_buf_out;
|
349 |
|
|
end if;
|
350 |
|
|
end if;
|
351 |
|
|
end if;
|
352 |
|
|
|
353 |
|
|
-- Latches the signals
|
354 |
|
|
NUMBER0 <= NUMBER0_sig;
|
355 |
|
|
NUMBER1 <= NUMBER1_sig;
|
356 |
|
|
NUMBER2 <= NUMBER2_sig;
|
357 |
|
|
NUMBER3 <= NUMBER3_sig;
|
358 |
|
|
LEDR(7 downto 0) <= LEDR_sig(7 downto 0);
|
359 |
|
|
LEDG <= LEDG_sig;
|
360 |
9 |
rrred |
|
361 |
2 |
rrred |
end process;
|
362 |
|
|
|
363 |
9 |
rrred |
|
364 |
2 |
rrred |
-- the following three processes deals with different clock domain signals
|
365 |
|
|
ps2_process1: process(CLOCK_50)
|
366 |
|
|
begin
|
367 |
|
|
if CLOCK_50'event and CLOCK_50 = '1' then
|
368 |
|
|
if ps2_read = '1' then
|
369 |
|
|
if ps2_ascii_sig /= x"FF" then
|
370 |
|
|
ps2_read <= '0';
|
371 |
|
|
ps2_ascii_reg1 <= "00000000";
|
372 |
|
|
end if;
|
373 |
|
|
elsif ps2_scan_ready = '1' then
|
374 |
|
|
if ps2_ascii_sig = x"FF" then
|
375 |
|
|
ps2_read <= '1';
|
376 |
|
|
else
|
377 |
|
|
ps2_ascii_reg1 <= ps2_ascii_sig;
|
378 |
|
|
end if;
|
379 |
|
|
end if;
|
380 |
|
|
end if;
|
381 |
|
|
end process;
|
382 |
|
|
|
383 |
|
|
ps2_process2: process(Clk_Z80)
|
384 |
|
|
begin
|
385 |
|
|
if Clk_Z80'event and Clk_Z80 = '1' then
|
386 |
|
|
ps2_ascii_reg <= ps2_ascii_reg1;
|
387 |
|
|
end if;
|
388 |
|
|
end process;
|
389 |
|
|
|
390 |
|
|
|
391 |
|
|
One <= '1';
|
392 |
|
|
Rst_n_s <= not SW(9);
|
393 |
|
|
|
394 |
|
|
z80_inst: T80s
|
395 |
|
|
port map (
|
396 |
|
|
M1_n => open,
|
397 |
|
|
MREQ_n => MReq_n,
|
398 |
|
|
IORQ_n => IORq_n,
|
399 |
|
|
RD_n => Rd_n,
|
400 |
|
|
WR_n => Wr_n,
|
401 |
|
|
RFSH_n => open,
|
402 |
|
|
HALT_n => open,
|
403 |
|
|
WAIT_n => One,
|
404 |
|
|
INT_n => One,
|
405 |
|
|
NMI_n => One,
|
406 |
|
|
RESET_n => Rst_n_s,
|
407 |
|
|
BUSRQ_n => One,
|
408 |
|
|
BUSAK_n => open,
|
409 |
|
|
CLK_n => Clk_Z80,
|
410 |
|
|
A => A,
|
411 |
|
|
DI => DI_CPU,
|
412 |
|
|
DO => DO_CPU
|
413 |
|
|
);
|
414 |
|
|
|
415 |
|
|
vga80x40_inst: work.video_80x40 port map (
|
416 |
|
|
CLOCK_50 => CLOCK_50,
|
417 |
|
|
VRAM_DATA => vram_q_sig,
|
418 |
|
|
VRAM_ADDR => vram_rdaddress_sig,
|
419 |
9 |
rrred |
VRAM_CLOCK => clk25mhz,
|
420 |
2 |
rrred |
VRAM_WREN => vram_rden_sig,
|
421 |
|
|
VGA_R => VGA_R,
|
422 |
|
|
VGA_G => VGA_G,
|
423 |
|
|
VGA_B => VGA_B,
|
424 |
|
|
VGA_HS => VGA_HS,
|
425 |
|
|
VGA_VS => VGA_VS
|
426 |
|
|
);
|
427 |
|
|
|
428 |
|
|
vram8k_inst : work.vram8k PORT MAP (
|
429 |
|
|
rdaddress => vram_rdaddress_sig,
|
430 |
9 |
rrred |
rdclock => not clk25mhz,
|
431 |
2 |
rrred |
rden => vram_rden_sig,
|
432 |
|
|
q => vram_q_sig,
|
433 |
|
|
wraddress => vram_wraddress_sig(12 downto 0),
|
434 |
|
|
wrclock => Clk_Z80,
|
435 |
|
|
wren => vram_wren_sig,
|
436 |
|
|
data => vram_data_sig
|
437 |
|
|
);
|
438 |
|
|
|
439 |
|
|
rom_inst: rom
|
440 |
|
|
port map (
|
441 |
|
|
Clk => Clk_Z80,
|
442 |
|
|
A => A,
|
443 |
|
|
D => D_ROM
|
444 |
|
|
);
|
445 |
9 |
rrred |
|
446 |
|
|
clkdiv_inst: clk_div
|
447 |
|
|
port map (
|
448 |
|
|
clock_25Mhz => clk25mhz,
|
449 |
|
|
clock_1MHz => open,
|
450 |
|
|
clock_100KHz => open,
|
451 |
|
|
clock_10KHz => open,
|
452 |
|
|
clock_1KHz => open,
|
453 |
|
|
clock_100Hz => clk100hz,
|
454 |
|
|
clock_10Hz => clk10hz,
|
455 |
|
|
clock_1Hz => clk1hz
|
456 |
|
|
);
|
457 |
|
|
|
458 |
2 |
rrred |
clock_z80_inst : Clock_357Mhz
|
459 |
|
|
port map (
|
460 |
|
|
clock_50Mhz => CLOCK_50,
|
461 |
|
|
clock_357Mhz => Clk_Z80
|
462 |
|
|
);
|
463 |
|
|
|
464 |
|
|
DISPHEX0 : decoder_7seg PORT MAP (
|
465 |
|
|
NUMBER => NUMBER0,
|
466 |
|
|
HEX_DISP => HEX_DISP0
|
467 |
|
|
);
|
468 |
|
|
|
469 |
|
|
DISPHEX1 : decoder_7seg PORT MAP (
|
470 |
|
|
NUMBER => NUMBER1,
|
471 |
|
|
HEX_DISP => HEX_DISP1
|
472 |
|
|
);
|
473 |
|
|
|
474 |
|
|
DISPHEX2 : decoder_7seg PORT MAP (
|
475 |
|
|
NUMBER => NUMBER2,
|
476 |
|
|
HEX_DISP => HEX_DISP2
|
477 |
|
|
);
|
478 |
|
|
|
479 |
|
|
DISPHEX3 : decoder_7seg PORT MAP (
|
480 |
|
|
NUMBER => NUMBER3,
|
481 |
|
|
HEX_DISP => HEX_DISP3
|
482 |
|
|
);
|
483 |
|
|
|
484 |
|
|
ps2_kbd_inst : work.ps2kbd PORT MAP (
|
485 |
|
|
keyboard_clk => PS2_CLK,
|
486 |
|
|
keyboard_data => PS2_DAT,
|
487 |
|
|
clock => CLOCK_50,
|
488 |
9 |
rrred |
clkdelay => clk100hz,
|
489 |
2 |
rrred |
reset => Rst_n_s,
|
490 |
|
|
read => ps2_read,
|
491 |
|
|
scan_ready => ps2_scan_ready,
|
492 |
|
|
ps2_ascii_code => ps2_ascii_sig
|
493 |
|
|
);
|
494 |
|
|
|
495 |
|
|
UART_TXD <= 'Z';
|
496 |
|
|
DRAM_ADDR <= (others => '0');
|
497 |
|
|
DRAM_LDQM <= '0';
|
498 |
|
|
DRAM_UDQM <= '0';
|
499 |
|
|
DRAM_WE_N <= '1';
|
500 |
|
|
DRAM_CAS_N <= '1';
|
501 |
|
|
DRAM_RAS_N <= '1';
|
502 |
|
|
DRAM_CS_N <= '1';
|
503 |
|
|
DRAM_BA_0 <= '0';
|
504 |
|
|
DRAM_BA_1 <= '0';
|
505 |
|
|
DRAM_CLK <= '0';
|
506 |
|
|
DRAM_CKE <= '0';
|
507 |
|
|
FL_ADDR <= (others => '0');
|
508 |
|
|
FL_WE_N <= '1';
|
509 |
|
|
FL_RST_N <= '0';
|
510 |
|
|
FL_OE_N <= '1';
|
511 |
|
|
FL_CE_N <= '1';
|
512 |
|
|
TDO <= '0';
|
513 |
|
|
I2C_SCLK <= '0';
|
514 |
|
|
AUD_DACDAT <= '0';
|
515 |
|
|
AUD_XCK <= '0';
|
516 |
|
|
-- Set all bidirectional ports to tri-state
|
517 |
|
|
DRAM_DQ <= (others => 'Z');
|
518 |
|
|
FL_DQ <= (others => 'Z');
|
519 |
|
|
I2C_SDAT <= 'Z';
|
520 |
|
|
AUD_ADCLRCK <= 'Z';
|
521 |
|
|
AUD_DACLRCK <= 'Z';
|
522 |
|
|
AUD_BCLK <= 'Z';
|
523 |
|
|
GPIO_0 <= (others => 'Z');
|
524 |
|
|
GPIO_1 <= (others => 'Z');
|
525 |
|
|
end;
|