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[/] [z80soc/] [tags/] [z80soc05b/] [rtl/] [VHDL/] [top_de1.vhd] - Blame information for rev 33

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-------------------------------------------------------------------------------------------------
-- Z80_Soc (Z80 System on Chip)
--
-- Version 0.5 Beta
--
-- Developer: Ronivon Candido Costa
-- Release Date: 2008 / 04 / 16
--
-- Based on the T80 core: http://www.opencores.org/projects.cgi/web/t80
-- This version developed and tested on: Altera DE1 Development Board
--
-- Please, see the RevisionHistory.txt file for complete features and change history.
--
-- Peripherals configured (Using Ports):
--
--      08 KB Internal ROM      Read            (0x0000h - 0x1FFFh)
--      08 KB INTERNAL VRAM     Write           (0x2000h - 0x3FFFh)
--      48 KB External SRAM     Read/Write      (0x4000h - 0xFFFFh)
--      08 Green Leds           Out             (Port 0x01h)
--      08 Red Leds                     Out             (Port 0x02h)
--      04 Seven Seg displays   Out             (Ports 0x10h and 0x11h)
--      36 Pins GPIO0           In/Out  (Ports 0xA0h, 0xA1h, 0xA2h, 0xA3h, 0xA4h, 0xC0h)
--      36 Pins GPIO1           In/Out  (Ports 0xB0h, 0xB1h, 0xB2h, 0xB3h, 0xB4h, 0xC1h)
--      08 Switches                     In              (Port 0x20h)
--      04 Push buttons         In              (Port 0x30h)
--      PS/2 keyboard           In              (Port 0x80h)
--      Video Out 40x30 (VGA)   Out             (0x2000h - 0x24B0)
--
-- TO-DO:
--      - Monitor program to introduce Z80 Assmebly codes and run
--      - Serial communication, to download assembly code from PC
--      - Add hardware support for 80x40 Video out
--      - SD/MMC card interface to read/store data and programs
-------------------------------------------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
 
entity  TOP_DE1 is
        port(
 
    -- Clocks
    CLOCK_27,                                      -- 27 MHz
    CLOCK_50,                                      -- 50 MHz
    EXT_CLOCK : in std_logic;                      -- External Clock
 
    -- Buttons and switches
    KEY : in std_logic_vector(3 downto 0);         -- Push buttons
    SW : in std_logic_vector(9 downto 0);          -- Switches
 
    -- LED displays
    HEX0, HEX1, HEX2, HEX3                         -- 7-segment displays
                        : out std_logic_vector(6 downto 0);
    LEDG : out std_logic_vector(7 downto 0);       -- Green LEDs
    LEDR : out std_logic_vector(9 downto 0);       -- Red LEDs
 
    -- RS-232 interface
    UART_TXD : out std_logic;                      -- UART transmitter   
    UART_RXD : in std_logic;                       -- UART receiver
 
    -- IRDA interface
 
    -- IRDA_TXD : out std_logic;                      -- IRDA Transmitter
    IRDA_RXD : in std_logic;                       -- IRDA Receiver
 
    -- SDRAM
    DRAM_DQ : inout std_logic_vector(15 downto 0); -- Data Bus
    DRAM_ADDR : out std_logic_vector(11 downto 0); -- Address Bus    
    DRAM_LDQM,                                     -- Low-byte Data Mask 
    DRAM_UDQM,                                     -- High-byte Data Mask
    DRAM_WE_N,                                     -- Write Enable
    DRAM_CAS_N,                                    -- Column Address Strobe
    DRAM_RAS_N,                                    -- Row Address Strobe
    DRAM_CS_N,                                     -- Chip Select
    DRAM_BA_0,                                     -- Bank Address 0
    DRAM_BA_1,                                     -- Bank Address 0
    DRAM_CLK,                                      -- Clock
    DRAM_CKE : out std_logic;                      -- Clock Enable
 
    -- FLASH
    FL_DQ : inout std_logic_vector(7 downto 0);      -- Data bus
    FL_ADDR : out std_logic_vector(21 downto 0);     -- Address bus
    FL_WE_N,                                         -- Write Enable
    FL_RST_N,                                        -- Reset
    FL_OE_N,                                         -- Output Enable
    FL_CE_N : out std_logic;                         -- Chip Enable
 
    -- SRAM
    SRAM_DQ : inout std_logic_vector(15 downto 0); -- Data bus 16 Bits
    SRAM_ADDR : out std_logic_vector(17 downto 0); -- Address bus 18 Bits
    SRAM_UB_N,                                     -- High-byte Data Mask 
    SRAM_LB_N,                                     -- Low-byte Data Mask 
    SRAM_WE_N,                                     -- Write Enable
    SRAM_CE_N,                                     -- Chip Enable
    SRAM_OE_N : out std_logic;                     -- Output Enable
 
    -- SD card interface
    SD_DAT : in std_logic;      -- SD Card Data      SD pin 7 "DAT 0/DataOut"
    SD_DAT3 : out std_logic;    -- SD Card Data 3    SD pin 1 "DAT 3/nCS"
    SD_CMD : out std_logic;     -- SD Card Command   SD pin 2 "CMD/DataIn"
    SD_CLK : out std_logic;     -- SD Card Clock     SD pin 5 "CLK"
 
    -- USB JTAG link
    TDI,                        -- CPLD -> FPGA (data in)
    TCK,                        -- CPLD -> FPGA (clk)
    TCS : in std_logic;         -- CPLD -> FPGA (CS)
    TDO : out std_logic;        -- FPGA -> CPLD (data out)
 
    -- I2C bus
    I2C_SDAT : inout std_logic; -- I2C Data
    I2C_SCLK : out std_logic;   -- I2C Clock
 
    -- PS/2 port
    PS2_DAT,                    -- Data
    PS2_CLK : inout std_logic;     -- Clock
 
    -- VGA output
    VGA_HS,                                             -- H_SYNC
    VGA_VS : out std_logic;                             -- SYNC
    VGA_R,                                              -- Red[3:0]
    VGA_G,                                              -- Green[3:0]
    VGA_B : out std_logic_vector(3 downto 0);           -- Blue[3:0]
 
    -- Audio CODEC
    AUD_ADCLRCK : inout std_logic;                      -- ADC LR Clock
    AUD_ADCDAT : in std_logic;                          -- ADC Data
    AUD_DACLRCK : inout std_logic;                      -- DAC LR Clock
    AUD_DACDAT : out std_logic;                         -- DAC Data
    AUD_BCLK : inout std_logic;                         -- Bit-Stream Clock
    AUD_XCK : out std_logic;                            -- Chip Clock
 
    -- General-purpose I/O
    GPIO_0,                                      -- GPIO Connection 0
    GPIO_1 : inout std_logic_vector(35 downto 0) -- GPIO Connection 1    
);
end TOP_DE1;
 
architecture rtl of TOP_DE1 is
 
        component T80s
        generic(
                Mode : integer := 0);
        port (
                RESET_n         : in std_logic;
                CLK_n           : in std_logic;
                WAIT_n          : in std_logic;
                INT_n           : in std_logic;
                NMI_n           : in std_logic;
                BUSRQ_n         : in std_logic;
                M1_n            : out std_logic;
                MREQ_n          : out std_logic;
                IORQ_n          : out std_logic;
                RD_n            : out std_logic;
                WR_n            : out std_logic;
                RFSH_n          : out std_logic;
                HALT_n          : out std_logic;
                BUSAK_n         : out std_logic;
                A                       : out std_logic_vector(15 downto 0);
                DI                      : in std_logic_vector(7 downto 0);
                DO                      : out std_logic_vector(7 downto 0));
        end component;
 
        component rom
        port (
                Clk     : in std_logic;
                A       : in std_logic_vector(15 downto 0);
                D       : out std_logic_vector(7 downto 0));
        end component;
 
        component Clock_357Mhz
        PORT (
                clock_50Mhz                             : IN    STD_LOGIC;
                clock_357Mhz                    : OUT   STD_LOGIC);
        end component;
 
        component clk_div
        PORT
        (
                clock_25Mhz                             : IN    STD_LOGIC;
                clock_1MHz                              : OUT   STD_LOGIC;
                clock_100KHz                    : OUT   STD_LOGIC;
                clock_10KHz                             : OUT   STD_LOGIC;
                clock_1KHz                              : OUT   STD_LOGIC;
                clock_100Hz                             : OUT   STD_LOGIC;
                clock_10Hz                              : OUT   STD_LOGIC;
                clock_1Hz                               : OUT   STD_LOGIC);
        end component;
 
        component decoder_7seg
        port (
                NUMBER          : in   std_logic_vector(3 downto 0);
                HEX_DISP        : out  std_logic_vector(6 downto 0));
        end component;
 
        signal MREQ_n   : std_logic;
        signal IORQ_n   : std_logic;
        signal RD_n             : std_logic;
        signal WR_n             : std_logic;
        signal MWr_n    : std_logic;
        signal Rst_n_s  : std_logic;
        signal Clk_Z80  : std_logic;
        signal DI_CPU   : std_logic_vector(7 downto 0);
        signal DO_CPU   : std_logic_vector(7 downto 0);
        signal A                : std_logic_vector(15 downto 0);
        signal One              : std_logic;
 
        signal D_ROM    : std_logic_vector(7 downto 0);
 
        signal clk25mhz_sig : std_logic;
        signal Clk_1hz          : std_logic;
 
        signal HEX_DISP0        : std_logic_vector(6 downto 0);
        signal HEX_DISP1        : std_logic_vector(6 downto 0);
        signal HEX_DISP2        : std_logic_vector(6 downto 0);
        signal HEX_DISP3        : std_logic_vector(6 downto 0);
 
        signal NUMBER0          : std_logic_vector(3 downto 0);
        signal NUMBER1          : std_logic_vector(3 downto 0);
        signal NUMBER2          : std_logic_vector(3 downto 0);
        signal NUMBER3          : std_logic_vector(3 downto 0);
 
        signal GPIO_0_buf_in    : std_logic_vector(35 downto 0);
        signal GPIO_1_buf_in    : std_logic_vector(35 downto 0);
 
        signal  vram_rdaddress_sig      : std_logic_vector(12 downto 0);
        signal  vram_wraddress_sig      : std_logic_vector(15 downto 0);
        signal  vram_data_sig           : std_logic_vector(7 downto 0);
        signal  vram_q_sig                      : std_logic_vector(7 downto 0);
        signal  vram_q_reg                      : std_logic_vector(7 downto 0);
        signal  vram_wren_sig           : std_logic;
        signal  vram_rden_sig           : std_logic;
        signal  vram_rdcycle_count      : std_logic_vector(3 downto 0);
        signal  vram_wrcycle_count      : std_logic_vector(3 downto 0);
        signal  VRAM_CLOCK                      : std_logic;
 
        -- PS/2 Keyboard
        signal ps2_read                         : std_logic;
        signal ps2_scan_ready           : std_logic;
        signal ps2_ascii_sig            : std_logic_vector(7 downto 0);
        signal ps2_ascii_reg1           : std_logic_vector(7 downto 0);
        signal ps2_ascii_reg            : std_logic_vector(7 downto 0);
 
begin
 
        HEX0 <= HEX_DISP0;
        HEX1 <= HEX_DISP1;
        HEX2 <= HEX_DISP2;
        HEX3 <= HEX_DISP3;
 
        SRAM_ADDR(15 downto 0) <= A - x"4000" when (A >= x"4000" and MReq_n = '0');
        SRAM_DQ(15 downto 8) <= (others => 'Z');
        SRAM_ADDR(17 downto 16) <= "00";
        SRAM_UB_N <= '1';
        SRAM_LB_N <= '0';
        SRAM_CE_N <= '0';
        SRAM_WE_N <= Wr_n or MReq_n when A >= x"4000";
        SRAM_OE_N <= Rd_n;
 
        -- Write to SRAM (0x4000 - 0xFFFF)
        SRAM_DQ(7 downto 0) <= DO_CPU when (Wr_n = '0' and MReq_n = '0' and A >= x"4000") else (others => 'Z');
 
        -- Write into VRAM
        vram_wraddress_sig <= A - x"2000" when (A >= x"2000" and A < x"4000" and MReq_n = '0');
        vram_wren_sig <= not Wr_n when (A >= x"2000" and A < x"4000" and IORQ_n = '1');
        vram_data_sig <= DO_CPU  when (Wr_n = '0' and MReq_n = '0' and A >= x"2000" and A < x"4000") else (others => 'Z');
 
        -- Input to Z80
        DI_CPU <= SRAM_DQ(7 downto 0) when (Rd_n = '0' and MReq_n = '0' and A >= x"4000") else
                        -- vram_q_sig when (A >= x"2000" and A < x"4000") else
                        D_ROM when (Rd_n = '0' and MReq_n = '0' and A < x"2000") else
                        SW(7 downto 0) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"20") else
                        ("0000" & KEY) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"30") else
                        GPIO_0(7 downto 0) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"A0") else
                        GPIO_0(15 downto 8) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"A1") else
                        GPIO_0(23 downto 16) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"A2") else
                        GPIO_0(31 downto 24) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"A3") else
                        ("0000" & GPIO_0(35 downto 32)) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"A4") else
                        GPIO_1(7 downto 0) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"B0") else
                        GPIO_1(15 downto 8) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"B1") else
                        GPIO_1(23 downto 16) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"B2") else
                        GPIO_1(31 downto 24) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"B3") else
                        ("0000" & GPIO_1(35 downto 32)) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"B4") else
                        ps2_ascii_reg when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"80");
 
        -- Process to latch leds and hex displays
        process(Clk_Z80)
        variable NUMBER0_sig    : std_logic_vector(3 downto 0);
        variable NUMBER1_sig    : std_logic_vector(3 downto 0);
        variable NUMBER2_sig    : std_logic_vector(3 downto 0);
        variable NUMBER3_sig    : std_logic_vector(3 downto 0);
        variable LEDG_sig               : std_logic_vector(7 downto 0);
        variable LEDR_sig               : std_logic_vector(9 downto 0);
 
        variable GPIO_0_buf_out: std_logic_vector(35 downto 0);
        variable GPIO_1_buf_out: std_logic_vector(35 downto 0);
 
        begin
 
                if Clk_Z80'event and Clk_Z80 = '1' then
                  if IORQ_n = '0' and Wr_n = '0' then
                        -- LEDG
                        if A(7 downto 0) = x"01" then
                                LEDG_sig := DO_CPU;
                        -- LEDR
                        elsif A(7 downto 0) = x"02" then
                                LEDR_sig(7 downto 0) := DO_CPU;
                        -- HEX1 and HEX0
                        elsif A(7 downto 0) = x"10" then
                                NUMBER0_sig := DO_CPU(3 downto 0);
                                NUMBER1_sig := DO_CPU(7 downto 4);
                        -- HEX3 and HEX2
                        elsif A(7 downto 0) = x"11" then
                                NUMBER2_sig := DO_CPU(3 downto 0);
                                NUMBER3_sig := DO_CPU(7 downto 4);
                        -- GPIO_0
                        elsif A(7 downto 0) = x"A0" then
                                GPIO_0_buf_out(7 downto 0)   := DO_CPU;
                        elsif A(7 downto 0) = x"A1" then
                                GPIO_0_buf_out(15 downto 8)  := DO_CPU;
                        elsif A(7 downto 0) = x"A2" then
                                GPIO_0_buf_out(23 downto 16) := DO_CPU;
                        elsif A(7 downto 0) = x"A3" then
                                GPIO_0_buf_out(31 downto 24) := DO_CPU;
                        elsif A(7 downto 0) = x"A4" then
                                GPIO_0_buf_out(35 downto 32) := DO_CPU(3 downto 0);
                        -- GPIO_1
                        elsif A(7 downto 0) = x"B0" then
                                GPIO_1_buf_out(7 downto 0)   := DO_CPU;
                        elsif A(7 downto 0) = x"B1" then
                                GPIO_1_buf_out(15 downto 8)  := DO_CPU;
                        elsif A(7 downto 0) = x"B2" then
                                GPIO_1_buf_out(23 downto 16) := DO_CPU;
                        elsif A(7 downto 0) = x"B3" then
                                GPIO_1_buf_out(31 downto 24) := DO_CPU;
                        elsif A(7 downto 0) = x"B4" then
                                GPIO_1_buf_out(35 downto 32) := DO_CPU(3 downto 0);
                        elsif A(7 downto 0) = x"C0" then
                                GPIO_0 <= GPIO_0_buf_out;
                        elsif A(7 downto 0) = x"C1" then
                                GPIO_1 <= GPIO_1_buf_out;
                        end if;
                  end if;
                end if;
 
                -- Latches the signals
                NUMBER0 <= NUMBER0_sig;
                NUMBER1 <= NUMBER1_sig;
                NUMBER2 <= NUMBER2_sig;
                NUMBER3 <= NUMBER3_sig;
                LEDR(7 downto 0) <= LEDR_sig(7 downto 0);
                LEDG <= LEDG_sig;
 
        end process;
 
        -- the following three processes deals with different clock domain signals
        ps2_process1: process(CLOCK_50)
        begin
                if CLOCK_50'event and CLOCK_50 = '1' then
                        if ps2_read = '1' then
                                if ps2_ascii_sig /= x"FF" then
                                        ps2_read <= '0';
                                        ps2_ascii_reg1 <= "00000000";
                                end if;
                        elsif ps2_scan_ready = '1' then
                                if ps2_ascii_sig = x"FF" then
                                        ps2_read <= '1';
                                else
                                        ps2_ascii_reg1 <= ps2_ascii_sig;
                                end if;
                        end if;
                end if;
        end process;
 
        ps2_process2: process(Clk_Z80)
        begin
                if Clk_Z80'event and Clk_Z80 = '1' then
                        ps2_ascii_reg <= ps2_ascii_reg1;
                end if;
        end process;
 
 
        One <= '1';
        Rst_n_s <= not SW(9);
 
        z80_inst: T80s
                port map (
                        M1_n => open,
                        MREQ_n => MReq_n,
                        IORQ_n => IORq_n,
                        RD_n => Rd_n,
                        WR_n => Wr_n,
                        RFSH_n => open,
                        HALT_n => open,
                        WAIT_n => One,
                        INT_n => One,
                        NMI_n => One,
                        RESET_n => Rst_n_s,
                        BUSRQ_n => One,
                        BUSAK_n => open,
                        CLK_n => Clk_Z80,
                        A => A,
                        DI => DI_CPU,
                        DO => DO_CPU
                );
 
        vga80x40_inst: work.video_80x40 port map (
                        CLOCK_50                => CLOCK_50,
                        VRAM_DATA               => vram_q_sig,
                        VRAM_ADDR               => vram_rdaddress_sig,
                        VRAM_CLOCK              => VRAM_CLOCK,
                        VRAM_WREN               => vram_rden_sig,
                        VGA_R                   => VGA_R,
                        VGA_G                   => VGA_G,
                        VGA_B                   => VGA_B,
                        VGA_HS                  => VGA_HS,
                        VGA_VS                  => VGA_VS
        );
 
        vram8k_inst : work.vram8k PORT MAP (
                rdaddress       => vram_rdaddress_sig,
                rdclock         => not VRAM_CLOCK,
                rden            => vram_rden_sig,
                q                       => vram_q_sig,
                wraddress       => vram_wraddress_sig(12 downto 0),
                wrclock         => Clk_Z80,
                wren            => vram_wren_sig,
                data            => vram_data_sig
        );
 
        rom_inst: rom
                port map (
                        Clk => Clk_Z80,
                        A       => A,
                        D       => D_ROM
                );
 
        clock_z80_inst : Clock_357Mhz
                port map (
                        clock_50Mhz             => CLOCK_50,
                        clock_357Mhz    => Clk_Z80
        );
 
        DISPHEX0 : decoder_7seg PORT MAP (
                NUMBER                  =>      NUMBER0,
                HEX_DISP                =>      HEX_DISP0
        );
 
        DISPHEX1 : decoder_7seg PORT MAP (
                NUMBER                  =>      NUMBER1,
                HEX_DISP                =>      HEX_DISP1
        );
 
        DISPHEX2 : decoder_7seg PORT MAP (
                NUMBER                  =>      NUMBER2,
                HEX_DISP                =>      HEX_DISP2
        );
 
        DISPHEX3 : decoder_7seg PORT MAP (
                NUMBER                  =>      NUMBER3,
                HEX_DISP                =>      HEX_DISP3
        );
 
        ps2_kbd_inst : work.ps2kbd PORT MAP (
                keyboard_clk    => PS2_CLK,
                keyboard_data   => PS2_DAT,
                clock                   => CLOCK_50,
                reset                   => Rst_n_s,
                read                    => ps2_read,
                scan_ready              => ps2_scan_ready,
                ps2_ascii_code  => ps2_ascii_sig
        );
 
        UART_TXD <= 'Z';
        DRAM_ADDR <= (others => '0');
        DRAM_LDQM <= '0';
        DRAM_UDQM <= '0';
        DRAM_WE_N <= '1';
        DRAM_CAS_N <= '1';
        DRAM_RAS_N <= '1';
        DRAM_CS_N <= '1';
        DRAM_BA_0 <= '0';
        DRAM_BA_1 <= '0';
        DRAM_CLK <= '0';
        DRAM_CKE <= '0';
        FL_ADDR <= (others => '0');
        FL_WE_N <= '1';
        FL_RST_N <= '0';
        FL_OE_N <= '1';
        FL_CE_N <= '1';
        TDO <= '0';
        I2C_SCLK <= '0';
        AUD_DACDAT <= '0';
        AUD_XCK <= '0';
        -- Set all bidirectional ports to tri-state
        DRAM_DQ     <= (others => 'Z');
        FL_DQ       <= (others => 'Z');
        I2C_SDAT    <= 'Z';
        AUD_ADCLRCK <= 'Z';
        AUD_DACLRCK <= 'Z';
        AUD_BCLK    <= 'Z';
        GPIO_0 <= (others => 'Z');
        GPIO_1 <= (others => 'Z');
end;

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[/] [z80soc/] [tags/] [z80soc05b/] [rtl/] [VHDL/] [top_de1.vhd] - Blame information for rev 33

Line No.	Rev	Author	Line
1	2	rrred	`-------------------------------------------------------------------------------------------------`
2			`-- Z80_Soc (Z80 System on Chip)`
3			`--`
4			`-- Version 0.5 Beta`
5			`--`
6			`-- Developer: Ronivon Candido Costa`
7			`-- Release Date: 2008 / 04 / 16`
8			`--`
9			`-- Based on the T80 core: http://www.opencores.org/projects.cgi/web/t80`
10			`-- This version developed and tested on: Altera DE1 Development Board`
11			`--`
12	4	rrred	`-- Please, see the RevisionHistory.txt file for complete features and change history.`
13			`--`
14	2	rrred	`-- Peripherals configured (Using Ports):`
15			`--`
16			`-- 08 KB Internal ROM Read (0x0000h - 0x1FFFh)`
17			`-- 08 KB INTERNAL VRAM Write (0x2000h - 0x3FFFh)`
18			`-- 48 KB External SRAM Read/Write (0x4000h - 0xFFFFh)`
19			`-- 08 Green Leds Out (Port 0x01h)`
20			`-- 08 Red Leds Out (Port 0x02h)`
21			`-- 04 Seven Seg displays Out (Ports 0x10h and 0x11h)`
22			`-- 36 Pins GPIO0 In/Out (Ports 0xA0h, 0xA1h, 0xA2h, 0xA3h, 0xA4h, 0xC0h)`
23			`-- 36 Pins GPIO1 In/Out (Ports 0xB0h, 0xB1h, 0xB2h, 0xB3h, 0xB4h, 0xC1h)`
24			`-- 08 Switches In (Port 0x20h)`
25			`-- 04 Push buttons In (Port 0x30h)`
26			`-- PS/2 keyboard In (Port 0x80h)`
27			`-- Video Out 40x30 (VGA) Out (0x2000h - 0x24B0)`
28			`--`
29			`-- TO-DO:`
30			`-- - Monitor program to introduce Z80 Assmebly codes and run`
31			`-- - Serial communication, to download assembly code from PC`
32			`-- - Add hardware support for 80x40 Video out`
33			`-- - SD/MMC card interface to read/store data and programs`
34			`-------------------------------------------------------------------------------------------------`
35
36			`library IEEE;`
37			`use IEEE.std_logic_1164.all;`
38			`use IEEE.std_logic_arith.all;`
39			`use IEEE.std_logic_unsigned.all;`
40
41			`entity TOP_DE1 is`
42			`port(`
43
44			`-- Clocks`
45			`CLOCK_27, -- 27 MHz`
46			`CLOCK_50, -- 50 MHz`
47			`EXT_CLOCK : in std_logic; -- External Clock`
48
49			`-- Buttons and switches`
50			`KEY : in std_logic_vector(3 downto 0); -- Push buttons`
51			`SW : in std_logic_vector(9 downto 0); -- Switches`
52
53			`-- LED displays`
54			`HEX0, HEX1, HEX2, HEX3 -- 7-segment displays`
55			`: out std_logic_vector(6 downto 0);`
56			`LEDG : out std_logic_vector(7 downto 0); -- Green LEDs`
57			`LEDR : out std_logic_vector(9 downto 0); -- Red LEDs`
58
59			`-- RS-232 interface`
60			`UART_TXD : out std_logic; -- UART transmitter`
61			`UART_RXD : in std_logic; -- UART receiver`
62
63			`-- IRDA interface`
64
65			`-- IRDA_TXD : out std_logic; -- IRDA Transmitter`
66			`IRDA_RXD : in std_logic; -- IRDA Receiver`
67
68			`-- SDRAM`
69			`DRAM_DQ : inout std_logic_vector(15 downto 0); -- Data Bus`
70			`DRAM_ADDR : out std_logic_vector(11 downto 0); -- Address Bus`
71			`DRAM_LDQM, -- Low-byte Data Mask`
72			`DRAM_UDQM, -- High-byte Data Mask`
73			`DRAM_WE_N, -- Write Enable`
74			`DRAM_CAS_N, -- Column Address Strobe`
75			`DRAM_RAS_N, -- Row Address Strobe`
76			`DRAM_CS_N, -- Chip Select`
77			`DRAM_BA_0, -- Bank Address 0`
78			`DRAM_BA_1, -- Bank Address 0`
79			`DRAM_CLK, -- Clock`
80			`DRAM_CKE : out std_logic; -- Clock Enable`
81
82			`-- FLASH`
83			`FL_DQ : inout std_logic_vector(7 downto 0); -- Data bus`
84			`FL_ADDR : out std_logic_vector(21 downto 0); -- Address bus`
85			`FL_WE_N, -- Write Enable`
86			`FL_RST_N, -- Reset`
87			`FL_OE_N, -- Output Enable`
88			`FL_CE_N : out std_logic; -- Chip Enable`
89
90			`-- SRAM`
91			`SRAM_DQ : inout std_logic_vector(15 downto 0); -- Data bus 16 Bits`
92			`SRAM_ADDR : out std_logic_vector(17 downto 0); -- Address bus 18 Bits`
93			`SRAM_UB_N, -- High-byte Data Mask`
94			`SRAM_LB_N, -- Low-byte Data Mask`
95			`SRAM_WE_N, -- Write Enable`
96			`SRAM_CE_N, -- Chip Enable`
97			`SRAM_OE_N : out std_logic; -- Output Enable`
98
99			`-- SD card interface`
100			`SD_DAT : in std_logic; -- SD Card Data SD pin 7 "DAT 0/DataOut"`
101			`SD_DAT3 : out std_logic; -- SD Card Data 3 SD pin 1 "DAT 3/nCS"`
102			`SD_CMD : out std_logic; -- SD Card Command SD pin 2 "CMD/DataIn"`
103			`SD_CLK : out std_logic; -- SD Card Clock SD pin 5 "CLK"`
104
105			`-- USB JTAG link`
106			`TDI, -- CPLD -> FPGA (data in)`
107			`TCK, -- CPLD -> FPGA (clk)`
108			`TCS : in std_logic; -- CPLD -> FPGA (CS)`
109			`TDO : out std_logic; -- FPGA -> CPLD (data out)`
110
111			`-- I2C bus`
112			`I2C_SDAT : inout std_logic; -- I2C Data`
113			`I2C_SCLK : out std_logic; -- I2C Clock`
114
115			`-- PS/2 port`
116			`PS2_DAT, -- Data`
117			`PS2_CLK : inout std_logic; -- Clock`
118
119			`-- VGA output`
120			`VGA_HS, -- H_SYNC`
121			`VGA_VS : out std_logic; -- SYNC`
122			`VGA_R, -- Red[3:0]`
123			`VGA_G, -- Green[3:0]`
124			`VGA_B : out std_logic_vector(3 downto 0); -- Blue[3:0]`
125
126			`-- Audio CODEC`
127			`AUD_ADCLRCK : inout std_logic; -- ADC LR Clock`
128			`AUD_ADCDAT : in std_logic; -- ADC Data`
129			`AUD_DACLRCK : inout std_logic; -- DAC LR Clock`
130			`AUD_DACDAT : out std_logic; -- DAC Data`
131			`AUD_BCLK : inout std_logic; -- Bit-Stream Clock`
132			`AUD_XCK : out std_logic; -- Chip Clock`
133
134			`-- General-purpose I/O`
135			`GPIO_0, -- GPIO Connection 0`
136			`GPIO_1 : inout std_logic_vector(35 downto 0) -- GPIO Connection 1`
137			`);`
138			`end TOP_DE1;`
139
140			`architecture rtl of TOP_DE1 is`
141
142			`component T80s`
143			`generic(`
144			`Mode : integer := 0);`
145			`port (`
146			`RESET_n : in std_logic;`
147			`CLK_n : in std_logic;`
148			`WAIT_n : in std_logic;`
149			`INT_n : in std_logic;`
150			`NMI_n : in std_logic;`
151			`BUSRQ_n : in std_logic;`
152			`M1_n : out std_logic;`
153			`MREQ_n : out std_logic;`
154			`IORQ_n : out std_logic;`
155			`RD_n : out std_logic;`
156			`WR_n : out std_logic;`
157			`RFSH_n : out std_logic;`
158			`HALT_n : out std_logic;`
159			`BUSAK_n : out std_logic;`
160			`A : out std_logic_vector(15 downto 0);`
161			`DI : in std_logic_vector(7 downto 0);`
162			`DO : out std_logic_vector(7 downto 0));`
163			`end component;`
164
165			`component rom`
166			`port (`
167			`Clk : in std_logic;`
168			`A : in std_logic_vector(15 downto 0);`
169			`D : out std_logic_vector(7 downto 0));`
170			`end component;`
171
172			`component Clock_357Mhz`
173			`PORT (`
174			`clock_50Mhz : IN STD_LOGIC;`
175			`clock_357Mhz : OUT STD_LOGIC);`
176			`end component;`
177
178			`component clk_div`
179			`PORT`
180			`(`
181			`clock_25Mhz : IN STD_LOGIC;`
182			`clock_1MHz : OUT STD_LOGIC;`
183			`clock_100KHz : OUT STD_LOGIC;`
184			`clock_10KHz : OUT STD_LOGIC;`
185			`clock_1KHz : OUT STD_LOGIC;`
186			`clock_100Hz : OUT STD_LOGIC;`
187			`clock_10Hz : OUT STD_LOGIC;`
188			`clock_1Hz : OUT STD_LOGIC);`
189			`end component;`
190
191			`component decoder_7seg`
192			`port (`
193			`NUMBER : in std_logic_vector(3 downto 0);`
194			`HEX_DISP : out std_logic_vector(6 downto 0));`
195			`end component;`
196
197			`signal MREQ_n : std_logic;`
198			`signal IORQ_n : std_logic;`
199			`signal RD_n : std_logic;`
200			`signal WR_n : std_logic;`
201			`signal MWr_n : std_logic;`
202			`signal Rst_n_s : std_logic;`
203			`signal Clk_Z80 : std_logic;`
204			`signal DI_CPU : std_logic_vector(7 downto 0);`
205			`signal DO_CPU : std_logic_vector(7 downto 0);`
206			`signal A : std_logic_vector(15 downto 0);`
207			`signal One : std_logic;`
208
209			`signal D_ROM : std_logic_vector(7 downto 0);`
210
211			`signal clk25mhz_sig : std_logic;`
212			`signal Clk_1hz : std_logic;`
213
214			`signal HEX_DISP0 : std_logic_vector(6 downto 0);`
215			`signal HEX_DISP1 : std_logic_vector(6 downto 0);`
216			`signal HEX_DISP2 : std_logic_vector(6 downto 0);`
217			`signal HEX_DISP3 : std_logic_vector(6 downto 0);`
218
219			`signal NUMBER0 : std_logic_vector(3 downto 0);`
220			`signal NUMBER1 : std_logic_vector(3 downto 0);`
221			`signal NUMBER2 : std_logic_vector(3 downto 0);`
222			`signal NUMBER3 : std_logic_vector(3 downto 0);`
223
224			`signal GPIO_0_buf_in : std_logic_vector(35 downto 0);`
225			`signal GPIO_1_buf_in : std_logic_vector(35 downto 0);`
226
227			`signal vram_rdaddress_sig : std_logic_vector(12 downto 0);`
228			`signal vram_wraddress_sig : std_logic_vector(15 downto 0);`
229			`signal vram_data_sig : std_logic_vector(7 downto 0);`
230			`signal vram_q_sig : std_logic_vector(7 downto 0);`
231			`signal vram_q_reg : std_logic_vector(7 downto 0);`
232			`signal vram_wren_sig : std_logic;`
233			`signal vram_rden_sig : std_logic;`
234			`signal vram_rdcycle_count : std_logic_vector(3 downto 0);`
235			`signal vram_wrcycle_count : std_logic_vector(3 downto 0);`
236			`signal VRAM_CLOCK : std_logic;`
237
238			`-- PS/2 Keyboard`
239			`signal ps2_read : std_logic;`
240			`signal ps2_scan_ready : std_logic;`
241			`signal ps2_ascii_sig : std_logic_vector(7 downto 0);`
242			`signal ps2_ascii_reg1 : std_logic_vector(7 downto 0);`
243			`signal ps2_ascii_reg : std_logic_vector(7 downto 0);`
244
245			`begin`
246
247			`HEX0 <= HEX_DISP0;`
248			`HEX1 <= HEX_DISP1;`
249			`HEX2 <= HEX_DISP2;`
250			`HEX3 <= HEX_DISP3;`
251
252			`SRAM_ADDR(15 downto 0) <= A - x"4000" when (A >= x"4000" and MReq_n = '0');`
253			`SRAM_DQ(15 downto 8) <= (others => 'Z');`
254			`SRAM_ADDR(17 downto 16) <= "00";`
255			`SRAM_UB_N <= '1';`
256			`SRAM_LB_N <= '0';`
257			`SRAM_CE_N <= '0';`
258			`SRAM_WE_N <= Wr_n or MReq_n when A >= x"4000";`
259			`SRAM_OE_N <= Rd_n;`
260
261			`-- Write to SRAM (0x4000 - 0xFFFF)`
262			`SRAM_DQ(7 downto 0) <= DO_CPU when (Wr_n = '0' and MReq_n = '0' and A >= x"4000") else (others => 'Z');`
263
264			`-- Write into VRAM`
265			`vram_wraddress_sig <= A - x"2000" when (A >= x"2000" and A < x"4000" and MReq_n = '0');`
266			`vram_wren_sig <= not Wr_n when (A >= x"2000" and A < x"4000" and IORQ_n = '1');`
267			`vram_data_sig <= DO_CPU when (Wr_n = '0' and MReq_n = '0' and A >= x"2000" and A < x"4000") else (others => 'Z');`
268
269			`-- Input to Z80`
270			`DI_CPU <= SRAM_DQ(7 downto 0) when (Rd_n = '0' and MReq_n = '0' and A >= x"4000") else`
271			`-- vram_q_sig when (A >= x"2000" and A < x"4000") else`
272			`D_ROM when (Rd_n = '0' and MReq_n = '0' and A < x"2000") else`
273			`SW(7 downto 0) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"20") else`
274			`("0000" & KEY) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"30") else`
275			`GPIO_0(7 downto 0) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"A0") else`
276			`GPIO_0(15 downto 8) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"A1") else`
277			`GPIO_0(23 downto 16) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"A2") else`
278			`GPIO_0(31 downto 24) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"A3") else`
279			`("0000" & GPIO_0(35 downto 32)) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"A4") else`
280			`GPIO_1(7 downto 0) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"B0") else`
281			`GPIO_1(15 downto 8) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"B1") else`
282			`GPIO_1(23 downto 16) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"B2") else`
283			`GPIO_1(31 downto 24) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"B3") else`
284			`("0000" & GPIO_1(35 downto 32)) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"B4") else`
285			`ps2_ascii_reg when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"80");`
286
287			`-- Process to latch leds and hex displays`
288			`process(Clk_Z80)`
289			`variable NUMBER0_sig : std_logic_vector(3 downto 0);`
290			`variable NUMBER1_sig : std_logic_vector(3 downto 0);`
291			`variable NUMBER2_sig : std_logic_vector(3 downto 0);`
292			`variable NUMBER3_sig : std_logic_vector(3 downto 0);`
293			`variable LEDG_sig : std_logic_vector(7 downto 0);`
294			`variable LEDR_sig : std_logic_vector(9 downto 0);`
295
296			`variable GPIO_0_buf_out: std_logic_vector(35 downto 0);`
297			`variable GPIO_1_buf_out: std_logic_vector(35 downto 0);`
298
299			`begin`
300
301			`if Clk_Z80'event and Clk_Z80 = '1' then`
302			`if IORQ_n = '0' and Wr_n = '0' then`
303			`-- LEDG`
304			`if A(7 downto 0) = x"01" then`
305			`LEDG_sig := DO_CPU;`
306			`-- LEDR`
307			`elsif A(7 downto 0) = x"02" then`
308			`LEDR_sig(7 downto 0) := DO_CPU;`
309			`-- HEX1 and HEX0`
310			`elsif A(7 downto 0) = x"10" then`
311			`NUMBER0_sig := DO_CPU(3 downto 0);`
312			`NUMBER1_sig := DO_CPU(7 downto 4);`
313			`-- HEX3 and HEX2`
314			`elsif A(7 downto 0) = x"11" then`
315			`NUMBER2_sig := DO_CPU(3 downto 0);`
316			`NUMBER3_sig := DO_CPU(7 downto 4);`
317			`-- GPIO_0`
318			`elsif A(7 downto 0) = x"A0" then`
319			`GPIO_0_buf_out(7 downto 0) := DO_CPU;`
320			`elsif A(7 downto 0) = x"A1" then`
321			`GPIO_0_buf_out(15 downto 8) := DO_CPU;`
322			`elsif A(7 downto 0) = x"A2" then`
323			`GPIO_0_buf_out(23 downto 16) := DO_CPU;`
324			`elsif A(7 downto 0) = x"A3" then`
325			`GPIO_0_buf_out(31 downto 24) := DO_CPU;`
326			`elsif A(7 downto 0) = x"A4" then`
327			`GPIO_0_buf_out(35 downto 32) := DO_CPU(3 downto 0);`
328			`-- GPIO_1`
329			`elsif A(7 downto 0) = x"B0" then`
330			`GPIO_1_buf_out(7 downto 0) := DO_CPU;`
331			`elsif A(7 downto 0) = x"B1" then`
332			`GPIO_1_buf_out(15 downto 8) := DO_CPU;`
333			`elsif A(7 downto 0) = x"B2" then`
334			`GPIO_1_buf_out(23 downto 16) := DO_CPU;`
335			`elsif A(7 downto 0) = x"B3" then`
336			`GPIO_1_buf_out(31 downto 24) := DO_CPU;`
337			`elsif A(7 downto 0) = x"B4" then`
338			`GPIO_1_buf_out(35 downto 32) := DO_CPU(3 downto 0);`
339			`elsif A(7 downto 0) = x"C0" then`
340			`GPIO_0 <= GPIO_0_buf_out;`
341			`elsif A(7 downto 0) = x"C1" then`
342			`GPIO_1 <= GPIO_1_buf_out;`
343			`end if;`
344			`end if;`
345			`end if;`
346
347			`-- Latches the signals`
348			`NUMBER0 <= NUMBER0_sig;`
349			`NUMBER1 <= NUMBER1_sig;`
350			`NUMBER2 <= NUMBER2_sig;`
351			`NUMBER3 <= NUMBER3_sig;`
352			`LEDR(7 downto 0) <= LEDR_sig(7 downto 0);`
353			`LEDG <= LEDG_sig;`
354
355			`end process;`
356
357			`-- the following three processes deals with different clock domain signals`
358			`ps2_process1: process(CLOCK_50)`
359			`begin`
360			`if CLOCK_50'event and CLOCK_50 = '1' then`
361			`if ps2_read = '1' then`
362			`if ps2_ascii_sig /= x"FF" then`
363			`ps2_read <= '0';`
364			`ps2_ascii_reg1 <= "00000000";`
365			`end if;`
366			`elsif ps2_scan_ready = '1' then`
367			`if ps2_ascii_sig = x"FF" then`
368			`ps2_read <= '1';`
369			`else`
370			`ps2_ascii_reg1 <= ps2_ascii_sig;`
371			`end if;`
372			`end if;`
373			`end if;`
374			`end process;`
375
376			`ps2_process2: process(Clk_Z80)`
377			`begin`
378			`if Clk_Z80'event and Clk_Z80 = '1' then`
379			`ps2_ascii_reg <= ps2_ascii_reg1;`
380			`end if;`
381			`end process;`
382
383
384			`One <= '1';`
385			`Rst_n_s <= not SW(9);`
386
387			`z80_inst: T80s`
388			`port map (`
389			`M1_n => open,`
390			`MREQ_n => MReq_n,`
391			`IORQ_n => IORq_n,`
392			`RD_n => Rd_n,`
393			`WR_n => Wr_n,`
394			`RFSH_n => open,`
395			`HALT_n => open,`
396			`WAIT_n => One,`
397			`INT_n => One,`
398			`NMI_n => One,`
399			`RESET_n => Rst_n_s,`
400			`BUSRQ_n => One,`
401			`BUSAK_n => open,`
402			`CLK_n => Clk_Z80,`
403			`A => A,`
404			`DI => DI_CPU,`
405			`DO => DO_CPU`
406			`);`
407
408			`vga80x40_inst: work.video_80x40 port map (`
409			`CLOCK_50 => CLOCK_50,`
410			`VRAM_DATA => vram_q_sig,`
411			`VRAM_ADDR => vram_rdaddress_sig,`
412			`VRAM_CLOCK => VRAM_CLOCK,`
413			`VRAM_WREN => vram_rden_sig,`
414			`VGA_R => VGA_R,`
415			`VGA_G => VGA_G,`
416			`VGA_B => VGA_B,`
417			`VGA_HS => VGA_HS,`
418			`VGA_VS => VGA_VS`
419			`);`
420
421			`vram8k_inst : work.vram8k PORT MAP (`
422			`rdaddress => vram_rdaddress_sig,`
423			`rdclock => not VRAM_CLOCK,`
424			`rden => vram_rden_sig,`
425			`q => vram_q_sig,`
426			`wraddress => vram_wraddress_sig(12 downto 0),`
427			`wrclock => Clk_Z80,`
428			`wren => vram_wren_sig,`
429			`data => vram_data_sig`
430			`);`
431
432			`rom_inst: rom`
433			`port map (`
434			`Clk => Clk_Z80,`
435			`A => A,`
436			`D => D_ROM`
437			`);`
438
439			`clock_z80_inst : Clock_357Mhz`
440			`port map (`
441			`clock_50Mhz => CLOCK_50,`
442			`clock_357Mhz => Clk_Z80`
443			`);`
444
445			`DISPHEX0 : decoder_7seg PORT MAP (`
446			`NUMBER => NUMBER0,`
447			`HEX_DISP => HEX_DISP0`
448			`);`
449
450			`DISPHEX1 : decoder_7seg PORT MAP (`
451			`NUMBER => NUMBER1,`
452			`HEX_DISP => HEX_DISP1`
453			`);`
454
455			`DISPHEX2 : decoder_7seg PORT MAP (`
456			`NUMBER => NUMBER2,`
457			`HEX_DISP => HEX_DISP2`
458			`);`
459
460			`DISPHEX3 : decoder_7seg PORT MAP (`
461			`NUMBER => NUMBER3,`
462			`HEX_DISP => HEX_DISP3`
463			`);`
464
465			`ps2_kbd_inst : work.ps2kbd PORT MAP (`
466			`keyboard_clk => PS2_CLK,`
467			`keyboard_data => PS2_DAT,`
468			`clock => CLOCK_50,`
469			`reset => Rst_n_s,`
470			`read => ps2_read,`
471			`scan_ready => ps2_scan_ready,`
472			`ps2_ascii_code => ps2_ascii_sig`
473			`);`
474
475			`UART_TXD <= 'Z';`
476			`DRAM_ADDR <= (others => '0');`
477			`DRAM_LDQM <= '0';`
478			`DRAM_UDQM <= '0';`
479			`DRAM_WE_N <= '1';`
480			`DRAM_CAS_N <= '1';`
481			`DRAM_RAS_N <= '1';`
482			`DRAM_CS_N <= '1';`
483			`DRAM_BA_0 <= '0';`
484			`DRAM_BA_1 <= '0';`
485			`DRAM_CLK <= '0';`
486			`DRAM_CKE <= '0';`
487			`FL_ADDR <= (others => '0');`
488			`FL_WE_N <= '1';`
489			`FL_RST_N <= '0';`
490			`FL_OE_N <= '1';`
491			`FL_CE_N <= '1';`
492			`TDO <= '0';`
493			`I2C_SCLK <= '0';`
494			`AUD_DACDAT <= '0';`
495			`AUD_XCK <= '0';`
496			`-- Set all bidirectional ports to tri-state`
497			`DRAM_DQ <= (others => 'Z');`
498			`FL_DQ <= (others => 'Z');`
499			`I2C_SDAT <= 'Z';`
500			`AUD_ADCLRCK <= 'Z';`
501			`AUD_DACLRCK <= 'Z';`
502			`AUD_BCLK <= 'Z';`
503			`GPIO_0 <= (others => 'Z');`
504			`GPIO_1 <= (others => 'Z');`
505			`end;`