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[/] [z80soc/] [trunk/] [V0.6/] [S3E/] [top_s3e.vhd] - Blame information for rev 40

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-------------------------------------------------------------------------------------------------
-- Z80_Soc (Z80 System on Chip)
-- 
-- Version history:
-------------------
-- version 0.6 for Spartan 3E
-- Release Date: 2008 / 05 / 21
--
-- Version 0.5 Beta for Spartan 3E
-- Developer: Ronivon Candido Costa
-- Release Date: 2008 / 05 / 01
--
-- Based on the T80 core: http://www.opencores.org/projects.cgi/web/t80
-- This version developed and tested on: Diligent Spartan 3E
--
-- Architecture of z80soc:
-- Processor: Z80 Processor (T80 core) Runnig at 3.58 Mhz (can be changed)
--
-- External devices/resources:
-- 
--      16 KB Internal ROM      Read                    (0x0000h - 0x3FFFh)
--      08 KB INTERNAL VRAM     Write                   (0x4000h - 0x5FFFh)
--      01 LCD display                  Out                     (0x7FE0h - 0x7FFFh)
-- 16 KB INTERNAL RAM   Read/Write      (0x8000h - 0xBFFFh)
--      08 Green Leds                   Out                     (Port 0x01h)
--      04 Switches                             In                              (Port 0x20h)
--      04 Push buttons         In                              (Port 0x30h)
-- 01   Rotary Knob                     In                              (Port 0x70h)
--      PS/2 keyboard                   In                              (Port 0x80h)
--      Video write                             Out                     (Port 0x90h)
--
--  Revision history:
--
-- 2008/05/20 - Modified RAM layout to support new and future improvements
--            - Added port 0x90 to write a character to video.
--            - Cursor x,y automatically updated after writing to port 0x90
--            - Added port 0x91 for video cursor X
--            - Added port 0x92 for video cursor Y
--                 - Updated ROM to demonstrate how to use these new resources
--            - Changed ROM to support 14 bit addresses (16 Kb)
--
-- 2008/05/12 - Added support for the Rotary Knob
--            - ROT_CENTER push button (Knob) reserved for RESET
--            - The four push buttons are now available for the user (Port 0x30)
--
-- 2008/05/11 - Fixed access to RAM and VRAM,
--              Released same ROM version for DE1 and S3E
--
-- 2008/05/01 - Added LCD support for Spartan 3E
--
-- 2008/04(21 - Release of Version 0.5-S3E-Beta for Diligent Spartan 3E
--
--      2008/04/17 - Added Video support for 40x30 mode
--
-- 2008/04/16 - Release of Version 0.5-DE1-Beta for Altera DE1
--
-- TO-DO:
-- - Implement hardware control for the A/D and IO pins
-- - Monitor program to introduce Z80 Assmebly codes and run
--      - Serial communication, to download assembly code from PC
--      - Add hardware support for 80x40 Video out
--      - SD/MMC card interface to read/store data and programs
-------------------------------------------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
 
entity Z80SOC_TOP is
        port(
    -- Clocks
    CLOCK_50 : in std_logic;                                    -- 50 MHz
 
    -- Buttons and switches
    KEY : in std_logic_vector(3 downto 0);         -- Push buttons
    SW : in std_logic_vector(3 downto 0);          -- Switches
 
    -- LED displays
    LEDG : out std_logic_vector(7 downto 0);       -- Green LEDs
 
    -- RS-232 interface
    -- UART_TXD : out std_logic;                      -- UART transmitter   
    -- UART_RXD : in std_logic;                       -- UART receiver
 
    -- PS/2 port
    PS2_DAT,                    -- Data
    PS2_CLK : inout std_logic;     -- Clock
 
    -- VGA output
    VGA_HS,                                             -- H_SYNC
    VGA_VS : out std_logic;                             -- SYNC
    VGA_R,                                              -- Red[3:0]
    VGA_G,                                              -- Green[3:0]
    VGA_B : out std_logic;                                                                         -- Blue[3:0]
         SF_D  : out std_logic_vector(3 downto 0);
         LCD_E, LCD_RS, LCD_RW, SF_CE0 : out std_logic;
         ROT_A, ROT_B, ROT_CENTER : in std_logic
);
end Z80SOC_TOP;
 
architecture rtl of Z80SOC_TOP is
 
        component T80se
        generic(
                Mode : integer := 0;     -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
                T2Write : integer := 1; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
                IOWait : integer := 1   -- 0 => Single cycle I/O, 1 => Std I/O cycle
        );
        port(
                RESET_n : in std_logic;
                CLK_n           : in std_logic;
                CLKEN           : in std_logic;
                WAIT_n  : in std_logic;
                INT_n           : in std_logic;
                NMI_n           : in std_logic;
                BUSRQ_n : in std_logic;
                M1_n            : out std_logic;
                MREQ_n  : out std_logic;
                IORQ_n  : out std_logic;
                RD_n            : out std_logic;
                WR_n            : out std_logic;
                RFSH_n  : out std_logic;
                HALT_n  : out std_logic;
                BUSAK_n : out std_logic;
                A                       : out std_logic_vector(15 downto 0);
                DI                      : in std_logic_vector(7 downto 0);
                DO                      : out std_logic_vector(7 downto 0)
        );
        end component;
 
        component sram16k
                port (
                addr    : IN std_logic_VECTOR(13 downto 0);
                clk     : IN std_logic;
                din     : IN std_logic_VECTOR(7 downto 0);
                dout    : OUT std_logic_VECTOR(7 downto 0);
                we              : IN std_logic);
        end component;
 
        component rom
        port (
                Clk     : in std_logic;
                A               : in std_logic_vector(13 downto 0);
                D               : out std_logic_vector(7 downto 0));
        end component;
 
        component Clock_357Mhz
        PORT (
                clock_50Mhz                             : IN    STD_LOGIC;
                clock_357Mhz                    : OUT   STD_LOGIC);
        end component;
 
        component clk_div
        PORT
        (
                clock_25Mhz                             : IN    STD_LOGIC;
                clock_1MHz                              : OUT   STD_LOGIC;
                clock_100KHz                    : OUT   STD_LOGIC;
                clock_10KHz                             : OUT   STD_LOGIC;
                clock_1KHz                              : OUT   STD_LOGIC;
                clock_100Hz                             : OUT   STD_LOGIC;
                clock_10Hz                              : OUT   STD_LOGIC;
                clock_1Hz                               : OUT   STD_LOGIC);
        end component;
 
        component lcd
        port(
                clk, reset                                                      : in std_logic;
                SF_D                                                                    : out std_logic_vector(3 downto 0);
                LCD_E, LCD_RS, LCD_RW, SF_CE0 : out std_logic;
                lcd_addr                                                                : out std_logic_vector(4 downto 0);
                lcd_char                                                                : in std_logic_vector(7 downto 0));
        end component;
 
        component lcdvram
        port (
                addra   : IN std_logic_VECTOR(4 downto 0);
                addrb   : IN std_logic_VECTOR(4 downto 0);
                clka    : IN std_logic;
                clkb    : IN std_logic;
                dina    : IN std_logic_VECTOR(7 downto 0);
                doutb   : OUT std_logic_VECTOR(7 downto 0);
                wea     : IN std_logic);
        end component;
 
        component ps2kbd
        PORT (
                        keyboard_clk    : inout std_logic;
                        keyboard_data   : inout std_logic;
                        clock                           : in std_logic;
                        clkdelay                        : in std_logic;
                        reset                           : in std_logic;
                        read                            : in std_logic;
                        scan_ready              : out std_logic;
                        ps2_ascii_code  : out std_logic_vector(7 downto 0));
        end component;
 
        component vram8k
        port (
                addra: IN std_logic_VECTOR(12 downto 0);
                addrb: IN std_logic_VECTOR(12 downto 0);
                clka: IN std_logic;
                clkb: IN std_logic;
                dina: IN std_logic_VECTOR(7 downto 0);
                dinb: IN std_logic_VECTOR(7 downto 0);
                douta: OUT std_logic_VECTOR(7 downto 0);
                doutb: OUT std_logic_VECTOR(7 downto 0);
                wea: IN std_logic;
                web: IN std_logic);
        end component;
 
        COMPONENT video
        PORT (
                        CLOCK_25                : IN STD_LOGIC;
                        VRAM_DATA       : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
                        VRAM_ADDR       : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
                        VRAM_CLOCK      : OUT STD_LOGIC;
                        VRAM_WREN       : OUT STD_LOGIC;
                        VGA_R,
                        VGA_G,
                        VGA_B                   : OUT STD_LOGIC;
                        VGA_HS,
                        VGA_VS          : OUT STD_LOGIC);
        END COMPONENT;
 
        COMPONENT ROT_CTRL
        PORT (
                CLOCK                           : IN STD_LOGIC;
                ROT_A                           : IN    STD_LOGIC;
                ROT_B                           : IN    STD_LOGIC;
                DIRECTION               : OUT   STD_LOGIC_VECTOR(1 DOWNTO 0));
        END COMPONENT;
 
        signal MREQ_n   : std_logic;
        signal IORQ_n   : std_logic;
        signal RD_n             : std_logic;
        signal WR_n             : std_logic;
        signal MWr_n    : std_logic;
        signal Rst_n_s  : std_logic;
        signal Clk_Z80  : std_logic;
        signal DI_CPU   : std_logic_vector(7 downto 0);
        signal DO_CPU   : std_logic_vector(7 downto 0);
        signal A                        : std_logic_vector(15 downto 0);
        signal One              : std_logic;
 
        signal D_ROM    : std_logic_vector(7 downto 0);
 
        signal clk25mhz         : std_logic;
        signal clk100hz         : std_logic;
        signal clk10hz                  : std_logic;
        signal clk1hz                   : std_logic;
 
        signal vram_addra               : std_logic_vector(15 downto 0);
        signal vram_addrb               : std_logic_vector(15 downto 0);
        signal vram_dina                        : std_logic_vector(7 downto 0);
        signal vram_dinb                        : std_logic_vector(7 downto 0);
        signal vram_douta               : std_logic_vector(7 downto 0);
        signal vram_doutb               : std_logic_vector(7 downto 0);
        signal vram_wea                 : std_logic;
        signal vram_web                 : std_logic;
        signal vram_clka                        : std_logic;
        signal vram_clkb                        : std_logic;
 
        signal vram_douta_reg   : std_logic_vector(7 downto 0);
        signal VID_CURSOR               : std_logic_vector(15 downto 0);
        signal CURSOR_X             : std_logic_vector(5 downto 0);
        signal CURSOR_Y             : std_logic_vector(4 downto 0);
 
        -- sram signals
        signal sram_addr                : std_logic_vector(15 downto 0);
        signal sram_din         : std_logic_vector(7 downto 0);
        signal sram_dout                : std_logic_vector(7 downto 0);
        signal sram_we                  : std_logic;
 
        -- LCD signals
        signal lcd_wea                  : std_logic;
        signal lcd_addra                : std_logic_vector(4 downto 0);
        signal lcd_addrb                : std_logic_vector(4 downto 0);
        signal lcd_dina         : std_logic_vector(7 downto 0);
        signal lcd_doutb                : std_logic_vector(7 downto 0);
 
        -- VGA conversion from 4 bits to 8 bit
        signal VGA_Rs, VGA_Gs, VGA_Bs   : std_logic_vector(3 downto 0);
        signal VGA_HSs, VGA_VSs                 : std_logic;
 
        -- PS/2 Keyboard
        signal ps2_read                                 : std_logic;
        signal ps2_scan_ready                   : std_logic;
        signal ps2_ascii_sig                            : std_logic_vector(7 downto 0);
        signal ps2_ascii_reg1                   : std_logic_vector(7 downto 0);
        signal ps2_ascii_reg                            : std_logic_vector(7 downto 0);
 
        -- Rotary Control
        signal rot_dir     : std_logic_vector(1 downto 0);
        signal rot_dir_sig : std_logic_vector(1 downto 0);
 
        signal Z80SOC_VERSION           : std_logic_vector(2 downto 0);   -- "000" = DE1, "001" = S3E
        signal Z80SOC_STACK                     : std_logic_vector(15 downto 0);  -- Should be set to top of (RAM Memory - 1)
 
begin
 
        Z80SOC_VERSION <= "001";                -- "000" = DE1, "001" = S3E
        Z80SOC_STACK <= x"BFFE";                -- Should be set to top of (RAM Memory - 1)     
        Rst_n_s <= not ROT_CENTER;
 
--      Write into VRAM
        vram_addra <= VID_CURSOR when (IORQ_n = '0' and MREQ_n = '1' and A(7 downto 0) = x"90")  else
                      A - x"4000" when (A >= x"4000" and A <= x"5FFF");
        vram_wea <= '0' when ((A >= x"4000" and A <= x"5FFF" and Wr_n = '0' and MReq_n = '0') or (Wr_n = '0' and IORQ_n = '0' and A(7 downto 0) = x"90")) else
                '1';
        vram_dina <= DO_CPU; -- when (A >= x"4000" and A <= x"5FFF" and Wr_n = '0' and MReq_n = '0');
 
-- Write into LCD video ram
        lcd_addra <= A - x"7FE0" when (A >= x"7FE0" and A <= x"7FFF");
        lcd_wea <= '0' when (A >= x"7FE0" and A <= x"7FFF" and Wr_n = '0' and MReq_n = '0') else '1';
        lcd_dina <= DO_CPU when (A >= x"7FE0" and A <= x"7FFF" and Wr_n = '0' and MReq_n = '0');
 
-- Write into SRAM
        sram_addr <= A - x"8000" when (A >= x"8000" and A <= x"BFFF");
        sram_we <= '0' when (A >= x"8000" and A <= x"BFFF" and Wr_n = '0' and MReq_n = '0') else '1';
        sram_din <= DO_CPU when (A >= x"8000" and A <= x"BFFF" and Wr_n = '0' and MReq_n = '0');
 
        DI_CPU <= ("00000" & Z80SOC_VERSION) when (Rd_n = '0' and MREQ_n = '0' and IORQ_n = '1' and A = x"7FDD") else
                        Z80SOC_STACK(7 downto 0) when (Rd_n = '0' and MREQ_n = '0' and IORQ_n = '1' and A = x"7FDE") else
                        Z80SOC_STACK(15 downto 8) when (Rd_n = '0' and MREQ_n = '0' and IORQ_n = '1' and A = x"7FDF") else
                        vram_douta when (MREQ_n = '0' and IORQ_n = '1' and Rd_n = '0' and A >= x"4000" and A <= x"5FFF") else
                   sram_dout when (Rd_n = '0' and MREQ_n = '0' and IORQ_n = '1' and A >= x"8000" and A <= x"BFFF") else
                        D_ROM when (Rd_n = '0' and MREQ_n = '0' and IORQ_n = '1' and A < x"4000") else
                        ("0000" & SW) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"20") else
                        ("0000" & KEY) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"30") else
                        ("000000" & rot_dir) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"70") else
                        ps2_ascii_reg when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"80") else
                        ("00" & CURSOR_X) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"91") else
                        ("000" & CURSOR_Y) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"92") else
                        "ZZZZZZZZ";
 
        -- Process to latch leds and hex displays
        pinout_process: process(Clk_Z80)
        variable LEDG_sig               : std_logic_vector(7 downto 0);
        begin
                if Clk_Z80'event and Clk_Z80 = '1' then
                  if IORQ_n = '0' and Wr_n = '0' then
                        -- LEDG
                        if A(7 downto 0) = x"01" then
                                LEDG_sig := DO_CPU;
                        end if;
                  end if;
                end if;
                -- Latches the signals
                LEDG <= LEDG_sig;
        end process;
 
        cursorxy: process (Clk_Z80)
        variable VID_X  : std_logic_vector(5 downto 0);
        variable VID_Y  : std_logic_vector(4 downto 0);
        begin
                if Clk_Z80'event and Clk_Z80 = '1' then
                        if (IORQ_n = '0' and MREQ_n = '1' and Wr_n = '0' and A(7 downto 0) = x"91") then
                                VID_X := DO_CPU(5 downto 0);
                        elsif (IORQ_n = '0' and MREQ_n = '1' and Wr_n = '0' and A(7 downto 0) = x"92") then
                                VID_Y := DO_CPU(4 downto 0);
                        elsif (IORQ_n = '0' and MREQ_n = '1' and Wr_n = '0' and A(7 downto 0) = x"90") then
                                if VID_X = "100111" then
                                        VID_X := "000000";
                                        if VID_Y = "11101" then
                                                VID_Y := "00000";
                                        else
                                                VID_Y := VID_Y + 1;
                                        end if;
                                else
                                        VID_X := VID_X + 1;
                                end if;
                        end if;
                end if;
                VID_CURSOR <= x"4000" + ( VID_X + ( VID_Y * "0101000"));
                CURSOR_X <= VID_X;
                CURSOR_Y <= VID_Y;
        end process;
 
        -- the following three processes deals with different clock domain signals
        ps2_process1: process(CLOCK_50)
        begin
                if CLOCK_50'event and CLOCK_50 = '1' then
                        if ps2_read = '1' then
                                if ps2_ascii_sig /= x"FF" then
                                        ps2_read <= '0';
                                        ps2_ascii_reg1 <= "00000000";
                                end if;
                        elsif ps2_scan_ready = '1' then
                                if ps2_ascii_sig = x"FF" then
                                        ps2_read <= '1';
                                else
                                        ps2_ascii_reg1 <= ps2_ascii_sig;
                                end if;
                        end if;
                end if;
        end process;
 
        ps2_process2: process(Clk_Z80)
        variable stack  : std_logic_vector(15 downto 0):=x"7FDE";
        begin
                if Clk_Z80'event and Clk_Z80 = '1' then
                        ps2_ascii_reg <= ps2_ascii_reg1;
                end if;
        end process;
 
        rot_process: process(clk100hz)
        begin
                if clk100hz'event and clk100hz = '1' then
                        rot_dir <= rot_dir_sig;
                end if;
        end process;
 
        One <= '1';
        z80_inst: T80se
                port map (
                        M1_n => open,
                        MREQ_n => MReq_n,
                        IORQ_n => IORq_n,
                        RD_n => Rd_n,
                        WR_n => Wr_n,
                        RFSH_n => open,
                        HALT_n => open,
                        WAIT_n => One,
                        INT_n => One,
                        NMI_n => One,
                        RESET_n => Rst_n_s,
                        BUSRQ_n => One,
                        BUSAK_n => open,
                        CLK_n => Clk_Z80,
                        CLKEN => One,
                        A => A,
                        DI => DI_CPU,
                        DO => DO_CPU
                );
 
        ps2_kbd_inst : ps2kbd PORT MAP (
                keyboard_clk    => PS2_CLK,
                keyboard_data   => PS2_DAT,
                clock                   => CLOCK_50,
                clkdelay                => clk100hz,
                reset                   => Rst_n_s,
                read                    => ps2_read,
                scan_ready              => ps2_scan_ready,
                ps2_ascii_code  => ps2_ascii_sig
        );
 
        clk25mhz_proc: process (CLOCK_50)
   begin
                if CLOCK_50'event and CLOCK_50 = '1' then
        clk25mhz <= not clk25mhz;
                end if;
   end process;
 
   clkdiv_inst: clk_div
                port map (
                clock_25Mhz             => clk25mhz,
                clock_1MHz              => open,
                clock_100KHz    => open,
                clock_10KHz             => open,
                clock_1KHz              => open,
                clock_100Hz             => clk100hz,
                clock_10Hz              => clk10hz,
                clock_1Hz               => clk1hz
        );
 
        clock_z80_inst : Clock_357Mhz
        port map (
                clock_50Mhz             => CLOCK_50,
                clock_357Mhz    => Clk_Z80
        );
 
        lcd_inst: lcd
        port map (
                clk                     => CLOCK_50,
                reset                   => not Rst_n_s,
                SF_D                    => SF_D,
                LCD_E                   => LCD_E,
                LCD_RS          => LCD_RS,
                LCD_RW          => LCD_RW,
                SF_CE0          => SF_CE0,
                lcd_addr                => lcd_addrb,
                lcd_char                => lcd_doutb
        );
 
        rom_inst: rom
                port map (
                        Clk => Clk_Z80,
                        A       => A(13 downto 0),
                        D       => D_ROM
                );
 
 
        video_inst: video port map (
                        CLOCK_25                        => clk25mhz,
                        VRAM_DATA               => vram_doutb,
                        VRAM_ADDR               => vram_addrb(12 downto 0),
                        VRAM_CLOCK              => vram_clkb,
                        VRAM_WREN               => vram_web,
                        VGA_R                           => VGA_R,
                        VGA_G                           => VGA_G,
                        VGA_B                           => VGA_B,
                        VGA_HS                  => VGA_HS,
                        VGA_VS                  => VGA_VS
        );
 
        vram8k_inst: vram8k port map (
                clka            => Clk_Z80,
                clkb            => vram_clkb,
      wea       => vram_wea,
                web     => vram_web,
      addra             => vram_addra(12 downto 0),
      addrb             => vram_addrb(12 downto 0),
      dina      => vram_dina,
      dinb      => vram_dinb,
                douta           => vram_douta,
                doutb           => vram_doutb
        );
 
        lcdvram_inst : lcdvram
                port map (
                        addra => lcd_addra,
                        addrb => lcd_addrb,
                        clka => Clk_Z80,
                        clkb => CLOCK_50,
                        dina => lcd_dina,
                        doutb => lcd_doutb,
                        wea => lcd_wea
                );
 
        ram16k_inst : sram16k
                port map (
                        addr => sram_addr(13 downto 0),
                        clk => Clk_Z80,
                        din => sram_din,
                        dout => sram_dout,
                        we => sram_we
        );
 
        rotary_inst: ROT_CTRL
                port map (
                        CLOCK                   => CLOCK_50,
                        ROT_A                   => ROT_A,
                        ROT_B                   => ROT_B,
                        DIRECTION       => rot_dir_sig
        );
 
end;

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[/] [z80soc/] [trunk/] [V0.6/] [S3E/] [top_s3e.vhd] - Blame information for rev 40

Line No.	Rev	Author	Line
1	40	rrred	`-------------------------------------------------------------------------------------------------`
2			`-- Z80_Soc (Z80 System on Chip)`
3			`--`
4			`-- Version history:`
5			`-------------------`
6			`-- version 0.6 for Spartan 3E`
7			`-- Release Date: 2008 / 05 / 21`
8			`--`
9			`-- Version 0.5 Beta for Spartan 3E`
10			`-- Developer: Ronivon Candido Costa`
11			`-- Release Date: 2008 / 05 / 01`
12			`--`
13			`-- Based on the T80 core: http://www.opencores.org/projects.cgi/web/t80`
14			`-- This version developed and tested on: Diligent Spartan 3E`
15			`--`
16			`-- Architecture of z80soc:`
17			`-- Processor: Z80 Processor (T80 core) Runnig at 3.58 Mhz (can be changed)`
18			`--`
19			`-- External devices/resources:`
20			`--`
21			`-- 16 KB Internal ROM Read (0x0000h - 0x3FFFh)`
22			`-- 08 KB INTERNAL VRAM Write (0x4000h - 0x5FFFh)`
23			`-- 01 LCD display Out (0x7FE0h - 0x7FFFh)`
24			`-- 16 KB INTERNAL RAM Read/Write (0x8000h - 0xBFFFh)`
25			`-- 08 Green Leds Out (Port 0x01h)`
26			`-- 04 Switches In (Port 0x20h)`
27			`-- 04 Push buttons In (Port 0x30h)`
28			`-- 01 Rotary Knob In (Port 0x70h)`
29			`-- PS/2 keyboard In (Port 0x80h)`
30			`-- Video write Out (Port 0x90h)`
31			`--`
32			`-- Revision history:`
33			`--`
34			`-- 2008/05/20 - Modified RAM layout to support new and future improvements`
35			`-- - Added port 0x90 to write a character to video.`
36			`-- - Cursor x,y automatically updated after writing to port 0x90`
37			`-- - Added port 0x91 for video cursor X`
38			`-- - Added port 0x92 for video cursor Y`
39			`-- - Updated ROM to demonstrate how to use these new resources`
40			`-- - Changed ROM to support 14 bit addresses (16 Kb)`
41			`--`
42			`-- 2008/05/12 - Added support for the Rotary Knob`
43			`-- - ROT_CENTER push button (Knob) reserved for RESET`
44			`-- - The four push buttons are now available for the user (Port 0x30)`
45			`--`
46			`-- 2008/05/11 - Fixed access to RAM and VRAM,`
47			`-- Released same ROM version for DE1 and S3E`
48			`--`
49			`-- 2008/05/01 - Added LCD support for Spartan 3E`
50			`--`
51			`-- 2008/04(21 - Release of Version 0.5-S3E-Beta for Diligent Spartan 3E`
52			`--`
53			`-- 2008/04/17 - Added Video support for 40x30 mode`
54			`--`
55			`-- 2008/04/16 - Release of Version 0.5-DE1-Beta for Altera DE1`
56			`--`
57			`-- TO-DO:`
58			`-- - Implement hardware control for the A/D and IO pins`
59			`-- - Monitor program to introduce Z80 Assmebly codes and run`
60			`-- - Serial communication, to download assembly code from PC`
61			`-- - Add hardware support for 80x40 Video out`
62			`-- - SD/MMC card interface to read/store data and programs`
63			`-------------------------------------------------------------------------------------------------`
64
65			`library IEEE;`
66			`use IEEE.std_logic_1164.all;`
67			`use IEEE.std_logic_unsigned.all;`
68			`use IEEE.numeric_std.all;`
69
70			`entity Z80SOC_TOP is`
71			`port(`
72			`-- Clocks`
73			`CLOCK_50 : in std_logic; -- 50 MHz`
74
75			`-- Buttons and switches`
76			`KEY : in std_logic_vector(3 downto 0); -- Push buttons`
77			`SW : in std_logic_vector(3 downto 0); -- Switches`
78
79			`-- LED displays`
80			`LEDG : out std_logic_vector(7 downto 0); -- Green LEDs`
81
82			`-- RS-232 interface`
83			`-- UART_TXD : out std_logic; -- UART transmitter`
84			`-- UART_RXD : in std_logic; -- UART receiver`
85
86			`-- PS/2 port`
87			`PS2_DAT, -- Data`
88			`PS2_CLK : inout std_logic; -- Clock`
89
90			`-- VGA output`
91			`VGA_HS, -- H_SYNC`
92			`VGA_VS : out std_logic; -- SYNC`
93			`VGA_R, -- Red[3:0]`
94			`VGA_G, -- Green[3:0]`
95			`VGA_B : out std_logic; -- Blue[3:0]`
96			`SF_D : out std_logic_vector(3 downto 0);`
97			`LCD_E, LCD_RS, LCD_RW, SF_CE0 : out std_logic;`
98			`ROT_A, ROT_B, ROT_CENTER : in std_logic`
99			`);`
100			`end Z80SOC_TOP;`
101
102			`architecture rtl of Z80SOC_TOP is`
103
104			`component T80se`
105			`generic(`
106			`Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB`
107			`T2Write : integer := 1; -- 0 => WR_n active in T3, /=0 => WR_n active in T2`
108			`IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle`
109			`);`
110			`port(`
111			`RESET_n : in std_logic;`
112			`CLK_n : in std_logic;`
113			`CLKEN : in std_logic;`
114			`WAIT_n : in std_logic;`
115			`INT_n : in std_logic;`
116			`NMI_n : in std_logic;`
117			`BUSRQ_n : in std_logic;`
118			`M1_n : out std_logic;`
119			`MREQ_n : out std_logic;`
120			`IORQ_n : out std_logic;`
121			`RD_n : out std_logic;`
122			`WR_n : out std_logic;`
123			`RFSH_n : out std_logic;`
124			`HALT_n : out std_logic;`
125			`BUSAK_n : out std_logic;`
126			`A : out std_logic_vector(15 downto 0);`
127			`DI : in std_logic_vector(7 downto 0);`
128			`DO : out std_logic_vector(7 downto 0)`
129			`);`
130			`end component;`
131
132			`component sram16k`
133			`port (`
134			`addr : IN std_logic_VECTOR(13 downto 0);`
135			`clk : IN std_logic;`
136			`din : IN std_logic_VECTOR(7 downto 0);`
137			`dout : OUT std_logic_VECTOR(7 downto 0);`
138			`we : IN std_logic);`
139			`end component;`
140
141			`component rom`
142			`port (`
143			`Clk : in std_logic;`
144			`A : in std_logic_vector(13 downto 0);`
145			`D : out std_logic_vector(7 downto 0));`
146			`end component;`
147
148			`component Clock_357Mhz`
149			`PORT (`
150			`clock_50Mhz : IN STD_LOGIC;`
151			`clock_357Mhz : OUT STD_LOGIC);`
152			`end component;`
153
154			`component clk_div`
155			`PORT`
156			`(`
157			`clock_25Mhz : IN STD_LOGIC;`
158			`clock_1MHz : OUT STD_LOGIC;`
159			`clock_100KHz : OUT STD_LOGIC;`
160			`clock_10KHz : OUT STD_LOGIC;`
161			`clock_1KHz : OUT STD_LOGIC;`
162			`clock_100Hz : OUT STD_LOGIC;`
163			`clock_10Hz : OUT STD_LOGIC;`
164			`clock_1Hz : OUT STD_LOGIC);`
165			`end component;`
166
167			`component lcd`
168			`port(`
169			`clk, reset : in std_logic;`
170			`SF_D : out std_logic_vector(3 downto 0);`
171			`LCD_E, LCD_RS, LCD_RW, SF_CE0 : out std_logic;`
172			`lcd_addr : out std_logic_vector(4 downto 0);`
173			`lcd_char : in std_logic_vector(7 downto 0));`
174			`end component;`
175
176			`component lcdvram`
177			`port (`
178			`addra : IN std_logic_VECTOR(4 downto 0);`
179			`addrb : IN std_logic_VECTOR(4 downto 0);`
180			`clka : IN std_logic;`
181			`clkb : IN std_logic;`
182			`dina : IN std_logic_VECTOR(7 downto 0);`
183			`doutb : OUT std_logic_VECTOR(7 downto 0);`
184			`wea : IN std_logic);`
185			`end component;`
186
187			`component ps2kbd`
188			`PORT (`
189			`keyboard_clk : inout std_logic;`
190			`keyboard_data : inout std_logic;`
191			`clock : in std_logic;`
192			`clkdelay : in std_logic;`
193			`reset : in std_logic;`
194			`read : in std_logic;`
195			`scan_ready : out std_logic;`
196			`ps2_ascii_code : out std_logic_vector(7 downto 0));`
197			`end component;`
198
199			`component vram8k`
200			`port (`
201			`addra: IN std_logic_VECTOR(12 downto 0);`
202			`addrb: IN std_logic_VECTOR(12 downto 0);`
203			`clka: IN std_logic;`
204			`clkb: IN std_logic;`
205			`dina: IN std_logic_VECTOR(7 downto 0);`
206			`dinb: IN std_logic_VECTOR(7 downto 0);`
207			`douta: OUT std_logic_VECTOR(7 downto 0);`
208			`doutb: OUT std_logic_VECTOR(7 downto 0);`
209			`wea: IN std_logic;`
210			`web: IN std_logic);`
211			`end component;`
212
213			`COMPONENT video`
214			`PORT (`
215			`CLOCK_25 : IN STD_LOGIC;`
216			`VRAM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
217			`VRAM_ADDR : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);`
218			`VRAM_CLOCK : OUT STD_LOGIC;`
219			`VRAM_WREN : OUT STD_LOGIC;`
220			`VGA_R,`
221			`VGA_G,`
222			`VGA_B : OUT STD_LOGIC;`
223			`VGA_HS,`
224			`VGA_VS : OUT STD_LOGIC);`
225			`END COMPONENT;`
226
227			`COMPONENT ROT_CTRL`
228			`PORT (`
229			`CLOCK : IN STD_LOGIC;`
230			`ROT_A : IN STD_LOGIC;`
231			`ROT_B : IN STD_LOGIC;`
232			`DIRECTION : OUT STD_LOGIC_VECTOR(1 DOWNTO 0));`
233			`END COMPONENT;`
234
235			`signal MREQ_n : std_logic;`
236			`signal IORQ_n : std_logic;`
237			`signal RD_n : std_logic;`
238			`signal WR_n : std_logic;`
239			`signal MWr_n : std_logic;`
240			`signal Rst_n_s : std_logic;`
241			`signal Clk_Z80 : std_logic;`
242			`signal DI_CPU : std_logic_vector(7 downto 0);`
243			`signal DO_CPU : std_logic_vector(7 downto 0);`
244			`signal A : std_logic_vector(15 downto 0);`
245			`signal One : std_logic;`
246
247			`signal D_ROM : std_logic_vector(7 downto 0);`
248
249			`signal clk25mhz : std_logic;`
250			`signal clk100hz : std_logic;`
251			`signal clk10hz : std_logic;`
252			`signal clk1hz : std_logic;`
253
254			`signal vram_addra : std_logic_vector(15 downto 0);`
255			`signal vram_addrb : std_logic_vector(15 downto 0);`
256			`signal vram_dina : std_logic_vector(7 downto 0);`
257			`signal vram_dinb : std_logic_vector(7 downto 0);`
258			`signal vram_douta : std_logic_vector(7 downto 0);`
259			`signal vram_doutb : std_logic_vector(7 downto 0);`
260			`signal vram_wea : std_logic;`
261			`signal vram_web : std_logic;`
262			`signal vram_clka : std_logic;`
263			`signal vram_clkb : std_logic;`
264
265			`signal vram_douta_reg : std_logic_vector(7 downto 0);`
266			`signal VID_CURSOR : std_logic_vector(15 downto 0);`
267			`signal CURSOR_X : std_logic_vector(5 downto 0);`
268			`signal CURSOR_Y : std_logic_vector(4 downto 0);`
269
270			`-- sram signals`
271			`signal sram_addr : std_logic_vector(15 downto 0);`
272			`signal sram_din : std_logic_vector(7 downto 0);`
273			`signal sram_dout : std_logic_vector(7 downto 0);`
274			`signal sram_we : std_logic;`
275
276			`-- LCD signals`
277			`signal lcd_wea : std_logic;`
278			`signal lcd_addra : std_logic_vector(4 downto 0);`
279			`signal lcd_addrb : std_logic_vector(4 downto 0);`
280			`signal lcd_dina : std_logic_vector(7 downto 0);`
281			`signal lcd_doutb : std_logic_vector(7 downto 0);`
282
283			`-- VGA conversion from 4 bits to 8 bit`
284			`signal VGA_Rs, VGA_Gs, VGA_Bs : std_logic_vector(3 downto 0);`
285			`signal VGA_HSs, VGA_VSs : std_logic;`
286
287			`-- PS/2 Keyboard`
288			`signal ps2_read : std_logic;`
289			`signal ps2_scan_ready : std_logic;`
290			`signal ps2_ascii_sig : std_logic_vector(7 downto 0);`
291			`signal ps2_ascii_reg1 : std_logic_vector(7 downto 0);`
292			`signal ps2_ascii_reg : std_logic_vector(7 downto 0);`
293
294			`-- Rotary Control`
295			`signal rot_dir : std_logic_vector(1 downto 0);`
296			`signal rot_dir_sig : std_logic_vector(1 downto 0);`
297
298			`signal Z80SOC_VERSION : std_logic_vector(2 downto 0); -- "000" = DE1, "001" = S3E`
299			`signal Z80SOC_STACK : std_logic_vector(15 downto 0); -- Should be set to top of (RAM Memory - 1)`
300
301			`begin`
302
303			`Z80SOC_VERSION <= "001"; -- "000" = DE1, "001" = S3E`
304			`Z80SOC_STACK <= x"BFFE"; -- Should be set to top of (RAM Memory - 1)`
305			`Rst_n_s <= not ROT_CENTER;`
306
307			`-- Write into VRAM`
308			`vram_addra <= VID_CURSOR when (IORQ_n = '0' and MREQ_n = '1' and A(7 downto 0) = x"90") else`
309			`A - x"4000" when (A >= x"4000" and A <= x"5FFF");`
310			`vram_wea <= '0' when ((A >= x"4000" and A <= x"5FFF" and Wr_n = '0' and MReq_n = '0') or (Wr_n = '0' and IORQ_n = '0' and A(7 downto 0) = x"90")) else`
311			`'1';`
312			`vram_dina <= DO_CPU; -- when (A >= x"4000" and A <= x"5FFF" and Wr_n = '0' and MReq_n = '0');`
313
314			`-- Write into LCD video ram`
315			`lcd_addra <= A - x"7FE0" when (A >= x"7FE0" and A <= x"7FFF");`
316			`lcd_wea <= '0' when (A >= x"7FE0" and A <= x"7FFF" and Wr_n = '0' and MReq_n = '0') else '1';`
317			`lcd_dina <= DO_CPU when (A >= x"7FE0" and A <= x"7FFF" and Wr_n = '0' and MReq_n = '0');`
318
319			`-- Write into SRAM`
320			`sram_addr <= A - x"8000" when (A >= x"8000" and A <= x"BFFF");`
321			`sram_we <= '0' when (A >= x"8000" and A <= x"BFFF" and Wr_n = '0' and MReq_n = '0') else '1';`
322			`sram_din <= DO_CPU when (A >= x"8000" and A <= x"BFFF" and Wr_n = '0' and MReq_n = '0');`
323
324			`DI_CPU <= ("00000" & Z80SOC_VERSION) when (Rd_n = '0' and MREQ_n = '0' and IORQ_n = '1' and A = x"7FDD") else`
325			`Z80SOC_STACK(7 downto 0) when (Rd_n = '0' and MREQ_n = '0' and IORQ_n = '1' and A = x"7FDE") else`
326			`Z80SOC_STACK(15 downto 8) when (Rd_n = '0' and MREQ_n = '0' and IORQ_n = '1' and A = x"7FDF") else`
327			`vram_douta when (MREQ_n = '0' and IORQ_n = '1' and Rd_n = '0' and A >= x"4000" and A <= x"5FFF") else`
328			`sram_dout when (Rd_n = '0' and MREQ_n = '0' and IORQ_n = '1' and A >= x"8000" and A <= x"BFFF") else`
329			`D_ROM when (Rd_n = '0' and MREQ_n = '0' and IORQ_n = '1' and A < x"4000") else`
330			`("0000" & SW) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"20") else`
331			`("0000" & KEY) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"30") else`
332			`("000000" & rot_dir) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"70") else`
333			`ps2_ascii_reg when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"80") else`
334			`("00" & CURSOR_X) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"91") else`
335			`("000" & CURSOR_Y) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"92") else`
336			`"ZZZZZZZZ";`
337
338			`-- Process to latch leds and hex displays`
339			`pinout_process: process(Clk_Z80)`
340			`variable LEDG_sig : std_logic_vector(7 downto 0);`
341			`begin`
342			`if Clk_Z80'event and Clk_Z80 = '1' then`
343			`if IORQ_n = '0' and Wr_n = '0' then`
344			`-- LEDG`
345			`if A(7 downto 0) = x"01" then`
346			`LEDG_sig := DO_CPU;`
347			`end if;`
348			`end if;`
349			`end if;`
350			`-- Latches the signals`
351			`LEDG <= LEDG_sig;`
352			`end process;`
353
354			`cursorxy: process (Clk_Z80)`
355			`variable VID_X : std_logic_vector(5 downto 0);`
356			`variable VID_Y : std_logic_vector(4 downto 0);`
357			`begin`
358			`if Clk_Z80'event and Clk_Z80 = '1' then`
359			`if (IORQ_n = '0' and MREQ_n = '1' and Wr_n = '0' and A(7 downto 0) = x"91") then`
360			`VID_X := DO_CPU(5 downto 0);`
361			`elsif (IORQ_n = '0' and MREQ_n = '1' and Wr_n = '0' and A(7 downto 0) = x"92") then`
362			`VID_Y := DO_CPU(4 downto 0);`
363			`elsif (IORQ_n = '0' and MREQ_n = '1' and Wr_n = '0' and A(7 downto 0) = x"90") then`
364			`if VID_X = "100111" then`
365			`VID_X := "000000";`
366			`if VID_Y = "11101" then`
367			`VID_Y := "00000";`
368			`else`
369			`VID_Y := VID_Y + 1;`
370			`end if;`
371			`else`
372			`VID_X := VID_X + 1;`
373			`end if;`
374			`end if;`
375			`end if;`
376			`VID_CURSOR <= x"4000" + ( VID_X + ( VID_Y * "0101000"));`
377			`CURSOR_X <= VID_X;`
378			`CURSOR_Y <= VID_Y;`
379			`end process;`
380
381			`-- the following three processes deals with different clock domain signals`
382			`ps2_process1: process(CLOCK_50)`
383			`begin`
384			`if CLOCK_50'event and CLOCK_50 = '1' then`
385			`if ps2_read = '1' then`
386			`if ps2_ascii_sig /= x"FF" then`
387			`ps2_read <= '0';`
388			`ps2_ascii_reg1 <= "00000000";`
389			`end if;`
390			`elsif ps2_scan_ready = '1' then`
391			`if ps2_ascii_sig = x"FF" then`
392			`ps2_read <= '1';`
393			`else`
394			`ps2_ascii_reg1 <= ps2_ascii_sig;`
395			`end if;`
396			`end if;`
397			`end if;`
398			`end process;`
399
400			`ps2_process2: process(Clk_Z80)`
401			`variable stack : std_logic_vector(15 downto 0):=x"7FDE";`
402			`begin`
403			`if Clk_Z80'event and Clk_Z80 = '1' then`
404			`ps2_ascii_reg <= ps2_ascii_reg1;`
405			`end if;`
406			`end process;`
407
408			`rot_process: process(clk100hz)`
409			`begin`
410			`if clk100hz'event and clk100hz = '1' then`
411			`rot_dir <= rot_dir_sig;`
412			`end if;`
413			`end process;`
414
415			`One <= '1';`
416			`z80_inst: T80se`
417			`port map (`
418			`M1_n => open,`
419			`MREQ_n => MReq_n,`
420			`IORQ_n => IORq_n,`
421			`RD_n => Rd_n,`
422			`WR_n => Wr_n,`
423			`RFSH_n => open,`
424			`HALT_n => open,`
425			`WAIT_n => One,`
426			`INT_n => One,`
427			`NMI_n => One,`
428			`RESET_n => Rst_n_s,`
429			`BUSRQ_n => One,`
430			`BUSAK_n => open,`
431			`CLK_n => Clk_Z80,`
432			`CLKEN => One,`
433			`A => A,`
434			`DI => DI_CPU,`
435			`DO => DO_CPU`
436			`);`
437
438			`ps2_kbd_inst : ps2kbd PORT MAP (`
439			`keyboard_clk => PS2_CLK,`
440			`keyboard_data => PS2_DAT,`
441			`clock => CLOCK_50,`
442			`clkdelay => clk100hz,`
443			`reset => Rst_n_s,`
444			`read => ps2_read,`
445			`scan_ready => ps2_scan_ready,`
446			`ps2_ascii_code => ps2_ascii_sig`
447			`);`
448
449			`clk25mhz_proc: process (CLOCK_50)`
450			`begin`
451			`if CLOCK_50'event and CLOCK_50 = '1' then`
452			`clk25mhz <= not clk25mhz;`
453			`end if;`
454			`end process;`
455
456			`clkdiv_inst: clk_div`
457			`port map (`
458			`clock_25Mhz => clk25mhz,`
459			`clock_1MHz => open,`
460			`clock_100KHz => open,`
461			`clock_10KHz => open,`
462			`clock_1KHz => open,`
463			`clock_100Hz => clk100hz,`
464			`clock_10Hz => clk10hz,`
465			`clock_1Hz => clk1hz`
466			`);`
467
468			`clock_z80_inst : Clock_357Mhz`
469			`port map (`
470			`clock_50Mhz => CLOCK_50,`
471			`clock_357Mhz => Clk_Z80`
472			`);`
473
474			`lcd_inst: lcd`
475			`port map (`
476			`clk => CLOCK_50,`
477			`reset => not Rst_n_s,`
478			`SF_D => SF_D,`
479			`LCD_E => LCD_E,`
480			`LCD_RS => LCD_RS,`
481			`LCD_RW => LCD_RW,`
482			`SF_CE0 => SF_CE0,`
483			`lcd_addr => lcd_addrb,`
484			`lcd_char => lcd_doutb`
485			`);`
486
487			`rom_inst: rom`
488			`port map (`
489			`Clk => Clk_Z80,`
490			`A => A(13 downto 0),`
491			`D => D_ROM`
492			`);`
493
494
495			`video_inst: video port map (`
496			`CLOCK_25 => clk25mhz,`
497			`VRAM_DATA => vram_doutb,`
498			`VRAM_ADDR => vram_addrb(12 downto 0),`
499			`VRAM_CLOCK => vram_clkb,`
500			`VRAM_WREN => vram_web,`
501			`VGA_R => VGA_R,`
502			`VGA_G => VGA_G,`
503			`VGA_B => VGA_B,`
504			`VGA_HS => VGA_HS,`
505			`VGA_VS => VGA_VS`
506			`);`
507
508			`vram8k_inst: vram8k port map (`
509			`clka => Clk_Z80,`
510			`clkb => vram_clkb,`
511			`wea => vram_wea,`
512			`web => vram_web,`
513			`addra => vram_addra(12 downto 0),`
514			`addrb => vram_addrb(12 downto 0),`
515			`dina => vram_dina,`
516			`dinb => vram_dinb,`
517			`douta => vram_douta,`
518			`doutb => vram_doutb`
519			`);`
520
521			`lcdvram_inst : lcdvram`
522			`port map (`
523			`addra => lcd_addra,`
524			`addrb => lcd_addrb,`
525			`clka => Clk_Z80,`
526			`clkb => CLOCK_50,`
527			`dina => lcd_dina,`
528			`doutb => lcd_doutb,`
529			`wea => lcd_wea`
530			`);`
531
532			`ram16k_inst : sram16k`
533			`port map (`
534			`addr => sram_addr(13 downto 0),`
535			`clk => Clk_Z80,`
536			`din => sram_din,`
537			`dout => sram_dout,`
538			`we => sram_we`
539			`);`
540
541			`rotary_inst: ROT_CTRL`
542			`port map (`
543			`CLOCK => CLOCK_50,`
544			`ROT_A => ROT_A,`
545			`ROT_B => ROT_B,`
546			`DIRECTION => rot_dir_sig`
547			`);`
548
549			`end;`