OpenCores
URL https://opencores.org/ocsvn/z80soc/z80soc/trunk

Subversion Repositories z80soc

[/] [z80soc/] [trunk/] [V0.7/] [S3E/] [memoryCores/] [ram24k.xco] - Blame information for rev 37

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 34 rrred
##############################################################
2
#
3
# Xilinx Core Generator version 11.1
4
# Date: Thu Feb 18 19:25:32 2010
5
#
6
##############################################################
7
#
8
#  This file contains the customisation parameters for a
9
#  Xilinx CORE Generator IP GUI. It is strongly recommended
10
#  that you do not manually alter this file as it may cause
11
#  unexpected and unsupported behavior.
12
#
13
##############################################################
14
#
15
# BEGIN Project Options
16
SET addpads = False
17
SET asysymbol = True
18
SET busformat = BusFormatAngleBracketNotRipped
19
SET createndf = False
20
SET designentry = VHDL
21
SET device = xc3s500e
22
SET devicefamily = spartan3e
23
SET flowvendor = Other
24
SET formalverification = False
25
SET foundationsym = False
26
SET implementationfiletype = Ngc
27
SET package = fg320
28
SET removerpms = False
29
SET simulationfiles = Behavioral
30
SET speedgrade = -4
31
SET verilogsim = False
32
SET vhdlsim = True
33
# END Project Options
34
# BEGIN Select
35
SELECT Block_Memory_Generator family Xilinx,_Inc. 3.1
36
# END Select
37
# BEGIN Parameters
38
CSET algorithm=Minimum_Area
39
CSET assume_synchronous_clk=false
40
CSET byte_size=9
41
CSET coe_file=no_coe_file_loaded
42
CSET collision_warnings=ALL
43
CSET component_name=ram24k
44
CSET disable_collision_warnings=false
45
CSET disable_out_of_range_warnings=false
46
CSET ecc=false
47
CSET enable_a=Always_Enabled
48
CSET enable_b=Always_Enabled
49
CSET error_injection_type=Single_Bit_Error_Injection
50
CSET fill_remaining_memory_locations=false
51
CSET load_init_file=false
52
CSET memory_type=Single_Port_RAM
53
CSET operating_mode_a=WRITE_FIRST
54
CSET operating_mode_b=WRITE_FIRST
55
CSET output_reset_value_a=0
56
CSET output_reset_value_b=0
57
CSET pipeline_stages=0
58
CSET primitive=8kx2
59
CSET read_width_a=8
60
CSET read_width_b=8
61
CSET register_porta_output_of_memory_core=false
62
CSET register_porta_output_of_memory_primitives=false
63
CSET register_portb_output_of_memory_core=false
64
CSET register_portb_output_of_memory_primitives=false
65
CSET remaining_memory_locations=0
66
CSET reset_memory_latch_a=false
67
CSET reset_memory_latch_b=false
68
CSET reset_priority_a=CE
69
CSET reset_priority_b=CE
70
CSET reset_type=SYNC
71
CSET use_byte_write_enable=false
72
CSET use_error_injection_pins=false
73
CSET use_ramb16bwer_reset_behavior=false
74
CSET use_regcea_pin=false
75
CSET use_regceb_pin=false
76
CSET use_rsta_pin=false
77
CSET use_rstb_pin=false
78
CSET write_depth_a=24576
79
CSET write_width_a=8
80
CSET write_width_b=8
81
# END Parameters
82
GENERATE
83
# CRC: 7d4cbb4c

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.