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[/] [z80soc/] [trunk/] [V0.7/] [S3E/] [memoryCores/] [z80socv0.7.cgp] - Blame information for rev 40

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Line No. Rev Author Line
1 34 rrred 
# Date: Thu Feb 18 17:31:51 2010
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SET addpads = False
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SET asysymbol = True
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = False
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SET designentry = VHDL
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SET device = xc3s500e
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SET devicefamily = spartan3e
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SET flowvendor = Other
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SET formalverification = False
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SET foundationsym = False
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SET implementationfiletype = Ngc
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SET package = fg320
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SET removerpms = False
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SET simulationfiles = Behavioral
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SET speedgrade = -4
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SET verilogsim = False
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SET vhdlsim = True
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SET workingdirectory = .\tmp\
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# CRC: f5ba11a6

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