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[/] [z80soc/] [trunk/] [V0.7/] [S3E/] [vhdl/] [lcd.vhd] - Blame information for rev 37

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-- lcd.vhd
-- Adapter by Ronivon C. costa - 2008/05/05 
--      Added two more states to the state machines (one for each lcd line)
--              Added RAM video (two ports) for the LCD
--              Changed logic to read RAM/write to LCD in loop
-----------------------------------------------------------
--Written by Rahul Vora
--for the University of New Mexico
--rhlvora@gmail.com
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity lcd is
        port(
        clk, reset : in std_logic;
        SF_D : out std_logic_vector(3 downto 0);
        LCD_E, LCD_RS, LCD_RW, SF_CE0 : out std_logic;
        lcd_addr        : out std_logic_vector(4 downto 0);
        lcd_char        : in std_logic_vector(7 downto 0));
end lcd;
 
architecture behavior of lcd is
 
type tx_sequence is (high_setup, high_hold, oneus, low_setup, low_hold, fortyus, done);
signal tx_state : tx_sequence := done;
signal tx_byte : std_logic_vector(7 downto 0);
signal tx_init : bit := '0';
 
type init_sequence is (idle, fifteenms, one, two, three, four, five, six, seven, eight, done);
signal init_state : init_sequence := idle;
signal init_init, init_done : bit := '0';
 
signal i : integer range 0 to 750000 := 0;
signal i2 : integer range 0 to 2000 := 0;
signal i3 : integer range 0 to 82000 := 0;
 
signal SF_D0, SF_D1 : std_logic_vector(3 downto 0);
signal LCD_E0, LCD_E1 : std_logic;
signal mux : std_logic;
 
type display_state is (init, function_set, entry_set, set_display, clr_display, pause, set_addr0, set_addr1, char_print0, char_print1, done);
signal cur_state : display_state := init;
 
signal lcd_addr_sig : std_logic_vector(4 downto 0);
 
begin
 
        lcd_addr <= lcd_addr_sig;
        SF_CE0 <= '1'; --disable intel strataflash
        LCD_RW <= '0'; --write only
 
        --The following "with" statements simplify the process of adding and removing states.
 
        --when to transmit a command/data and when not to
        with cur_state select
                tx_init <= '0' when init | pause | done,
                        '1' when others;
 
        --control the bus
        with cur_state select
                mux <= '1' when init,
                        '0' when others;
 
        --control the initialization sequence
        with cur_state select
                init_init <= '1' when init,
                        '0' when others;
 
        --register select
        with cur_state select
                LCD_RS <= '0' when function_set|entry_set|set_display|clr_display|set_addr0|set_addr1,
                        '1' when others;
 
        --what byte to transmit to lcd
        --refer to datasheet for an explanation of these values
        with cur_state select
                tx_byte <= "00101000" when function_set,
                        "00000110" when entry_set,
                        "00001100" when set_display,
                        "00000001" when clr_display,
                        "10000000" when set_addr0,
                        "11000000" when set_addr1,
                        lcd_char   when char_print0|char_print1,
                        "00000000" when others;
 
        --main state machine
        display: process(clk, reset)
        begin
                if(reset='1') then
                        cur_state <= function_set;
                elsif(clk='1' and clk'event) then
                        case cur_state is
                                --refer to intialize state machine below
                                when init =>
                                        if(init_done = '1') then
                                                cur_state <= function_set;
                                        else
                                                cur_state <= init;
                                        end if;
 
                                --every other state but pause uses the transmit state machine
                                when function_set =>
                                        if(i2 = 2000) then
                                                cur_state <= entry_set;
                                        else
                                                cur_state <= function_set;
                                        end if;
 
                                when entry_set =>
                                        if(i2 = 2000) then
                                                cur_state <= set_display;
                                        else
                                                cur_state <= entry_set;
                                        end if;
 
                                when set_display =>
                                        if(i2 = 2000) then
                                                cur_state <= clr_display;
                                        else
                                                cur_state <= set_display;
                                        end if;
 
                                when clr_display =>
                                        i3 <= 0;
                                        if(i2 = 2000) then
                                                cur_state <= pause;
                                        else
                                                cur_state <= clr_display;
                                        end if;
 
                                when pause =>
                                        if(i3 = 82000) then
                                                cur_state <= set_addr0;
                                                i3 <= 0;
                                        else
                                                cur_state <= pause;
                                                i3 <= i3 + 1;
                                        end if;
 
                                when set_addr0 =>
                                        if(i2 = 2000) then
                                                cur_state <= char_print0;
                                                lcd_addr_sig <= "00000";
                                        else
                                                cur_state <= set_addr0;
                                        end if;
 
                                when set_addr1 =>
                                        if(i2 = 2000) then
                                                cur_state <= char_print1;
                                                lcd_addr_sig <= "10000";
                                        else
                                                cur_state <= set_addr1;
                                        end if;
 
                                when char_print0 =>
                                        if(i2 = 2000) then
                                                if lcd_addr_sig = "01111" then
                                                        cur_state <= set_addr1;
                                                else
                                                        cur_state <= char_print0;
                                                        lcd_addr_sig <= lcd_addr_sig + 1;
                                                end if;
                                        else
                                                cur_state <= char_print0;
                                        end if;
 
                                when char_print1 =>
                                        if(i2 = 2000) then
                                                if lcd_addr_sig = "11111" then
                                                        cur_state <= set_addr0;
                                                else
                                                        cur_state <= char_print1;
                                                        lcd_addr_sig <= lcd_addr_sig + 1;
                                                end if;
                                        else
                                                cur_state <= char_print1;
                                        end if;
 
                                when done =>
                                        cur_state <= done;
                        end case;
                end if;
        end process display;
 
        with mux select
                SF_D <= SF_D0 when '0', --transmit
                        SF_D1 when others;      --initialize
        with mux select
                LCD_E <= LCD_E0 when '0', --transmit
                        LCD_E1 when others; --initialize
 
        --specified by datasheet
        transmit : process(clk, reset, tx_init)
        begin
                if(reset='1') then
                        tx_state <= done;
                elsif(clk='1' and clk'event) then
                        case tx_state is
                                when high_setup => --40ns
                                        LCD_E0 <= '0';
                                        SF_D0 <= tx_byte(7 downto 4);
                                        if(i2 = 2) then
                                                tx_state <= high_hold;
                                                i2 <= 0;
                                        else
                                                tx_state <= high_setup;
                                                i2 <= i2 + 1;
                                        end if;
 
                                when high_hold => --230ns
                                        LCD_E0 <= '1';
                                        SF_D0 <= tx_byte(7 downto 4);
                                        if(i2 = 12) then
                                                tx_state <= oneus;
                                                i2 <= 0;
                                        else
                                                tx_state <= high_hold;
                                                i2 <= i2 + 1;
                                        end if;
 
                                when oneus =>
                                        LCD_E0 <= '0';
                                        if(i2 = 50) then
                                                tx_state <= low_setup;
                                                i2 <= 0;
                                        else
                                                tx_state <= oneus;
                                                i2 <= i2 + 1;
                                        end if;
 
                                when low_setup =>
                                        LCD_E0 <= '0';
                                        SF_D0 <= tx_byte(3 downto 0);
                                        if(i2 = 2) then
                                                tx_state <= low_hold;
                                                i2 <= 0;
                                        else
                                                tx_state <= low_setup;
                                                i2 <= i2 + 1;
                                        end if;
 
                                when low_hold =>
                                        LCD_E0 <= '1';
                                        SF_D0 <= tx_byte(3 downto 0);
                                        if(i2 = 12) then
                                                tx_state <= fortyus;
                                                i2 <= 0;
                                        else
                                                tx_state <= low_hold;
                                                i2 <= i2 + 1;
                                        end if;
 
                                when fortyus =>
                                        LCD_E0 <= '0';
                                        if(i2 = 2000) then
                                                tx_state <= done;
                                                i2 <= 0;
                                        else
                                                tx_state <= fortyus;
                                                i2 <= i2 + 1;
                                        end if;
 
                                when done =>
                                        LCD_E0 <= '0';
                                        if(tx_init = '1') then
                                                tx_state <= high_setup;
                                                i2 <= 0;
                                        else
                                                tx_state <= done;
                                                i2 <= 0;
                                        end if;
 
                        end case;
                end if;
        end process transmit;
 
        --specified by datasheet
        power_on_initialize: process(clk, reset, init_init) --power on initialization sequence
        begin
                if(reset='1') then
                        init_state <= idle;
                        init_done <= '0';
                elsif(clk='1' and clk'event) then
                        case init_state is
                                when idle =>
                                        init_done <= '0';
                                        if(init_init = '1') then
                                                init_state <= fifteenms;
                                                i <= 0;
                                        else
                                                init_state <= idle;
                                                i <= i + 1;
                                        end if;
 
                                when fifteenms =>
                                        init_done <= '0';
                                        if(i = 750000) then
                                                init_state <= one;
                                                i <= 0;
                                        else
                                                init_state <= fifteenms;
                                                i <= i + 1;
                                        end if;
 
                                when one =>
                                        SF_D1 <= "0011";
                                        LCD_E1 <= '1';
                                        init_done <= '0';
                                        if(i = 11) then
                                                init_state<=two;
                                                i <= 0;
                                        else
                                                init_state<=one;
                                                i <= i + 1;
                                        end if;
 
                                when two =>
                                        LCD_E1 <= '0';
                                        init_done <= '0';
                                        if(i = 205000) then
                                                init_state<=three;
                                                i <= 0;
                                        else
                                                init_state<=two;
                                                i <= i + 1;
                                        end if;
 
                                when three =>
                                        SF_D1 <= "0011";
                                        LCD_E1 <= '1';
                                        init_done <= '0';
                                        if(i = 11) then
                                                init_state<=four;
                                                i <= 0;
                                        else
                                                init_state<=three;
                                                i <= i + 1;
                                        end if;
 
                                when four =>
                                        LCD_E1 <= '0';
                                        init_done <= '0';
                                        if(i = 5000) then
                                                init_state<=five;
                                                i <= 0;
                                        else
                                                init_state<=four;
                                                i <= i + 1;
                                        end if;
 
                                when five =>
                                        SF_D1 <= "0011";
                                        LCD_E1 <= '1';
                                        init_done <= '0';
                                        if(i = 11) then
                                                init_state<=six;
                                                i <= 0;
                                        else
                                                init_state<=five;
                                                i <= i + 1;
                                        end if;
 
                                when six =>
                                        LCD_E1 <= '0';
                                        init_done <= '0';
                                        if(i = 2000) then
                                                init_state<=seven;
                                                i <= 0;
                                        else
                                                init_state<=six;
                                                i <= i + 1;
                                        end if;
 
                                when seven =>
                                        SF_D1 <= "0010";
                                        LCD_E1 <= '1';
                                        init_done <= '0';
                                        if(i = 11) then
                                                init_state<=eight;
                                                i <= 0;
                                        else
                                                init_state<=seven;
                                                i <= i + 1;
                                        end if;
 
                                when eight =>
                                        LCD_E1 <= '0';
                                        init_done <= '0';
                                        if(i = 2000) then
                                                init_state<=done;
                                                i <= 0;
                                        else
                                                init_state<=eight;
                                                i <= i + 1;
                                        end if;
 
                                when done =>
                                        init_state <= done;
                                        init_done <= '1';
 
                        end case;
 
                end if;
        end process power_on_initialize;
 
end behavior;

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[/] [z80soc/] [trunk/] [V0.7/] [S3E/] [vhdl/] [lcd.vhd] - Blame information for rev 37

Line No.	Rev	Author	Line
1	34	rrred	`-- lcd.vhd`
2			`-- Adapter by Ronivon C. costa - 2008/05/05`
3			`-- Added two more states to the state machines (one for each lcd line)`
4			`-- Added RAM video (two ports) for the LCD`
5			`-- Changed logic to read RAM/write to LCD in loop`
6			`-----------------------------------------------------------`
7			`--Written by Rahul Vora`
8			`--for the University of New Mexico`
9			`--rhlvora@gmail.com`
10
11			`library IEEE;`
12			`use IEEE.STD_LOGIC_1164.ALL;`
13			`use IEEE.STD_LOGIC_ARITH.ALL;`
14			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
15
16			`---- Uncomment the following library declaration if instantiating`
17			`---- any Xilinx primitives in this code.`
18			`--library UNISIM;`
19			`--use UNISIM.VComponents.all;`
20
21			`entity lcd is`
22			`port(`
23			`clk, reset : in std_logic;`
24			`SF_D : out std_logic_vector(3 downto 0);`
25			`LCD_E, LCD_RS, LCD_RW, SF_CE0 : out std_logic;`
26			`lcd_addr : out std_logic_vector(4 downto 0);`
27			`lcd_char : in std_logic_vector(7 downto 0));`
28			`end lcd;`
29
30			`architecture behavior of lcd is`
31
32			`type tx_sequence is (high_setup, high_hold, oneus, low_setup, low_hold, fortyus, done);`
33			`signal tx_state : tx_sequence := done;`
34			`signal tx_byte : std_logic_vector(7 downto 0);`
35			`signal tx_init : bit := '0';`
36
37			`type init_sequence is (idle, fifteenms, one, two, three, four, five, six, seven, eight, done);`
38			`signal init_state : init_sequence := idle;`
39			`signal init_init, init_done : bit := '0';`
40
41			`signal i : integer range 0 to 750000 := 0;`
42			`signal i2 : integer range 0 to 2000 := 0;`
43			`signal i3 : integer range 0 to 82000 := 0;`
44
45			`signal SF_D0, SF_D1 : std_logic_vector(3 downto 0);`
46			`signal LCD_E0, LCD_E1 : std_logic;`
47			`signal mux : std_logic;`
48
49			`type display_state is (init, function_set, entry_set, set_display, clr_display, pause, set_addr0, set_addr1, char_print0, char_print1, done);`
50			`signal cur_state : display_state := init;`
51
52			`signal lcd_addr_sig : std_logic_vector(4 downto 0);`
53
54			`begin`
55
56			`lcd_addr <= lcd_addr_sig;`
57			`SF_CE0 <= '1'; --disable intel strataflash`
58			`LCD_RW <= '0'; --write only`
59
60			`--The following "with" statements simplify the process of adding and removing states.`
61
62			`--when to transmit a command/data and when not to`
63			`with cur_state select`
64			`tx_init <= '0' when init \| pause \| done,`
65			`'1' when others;`
66
67			`--control the bus`
68			`with cur_state select`
69			`mux <= '1' when init,`
70			`'0' when others;`
71
72			`--control the initialization sequence`
73			`with cur_state select`
74			`init_init <= '1' when init,`
75			`'0' when others;`
76
77			`--register select`
78			`with cur_state select`
79			`LCD_RS <= '0' when function_set\|entry_set\|set_display\|clr_display\|set_addr0\|set_addr1,`
80			`'1' when others;`
81
82			`--what byte to transmit to lcd`
83			`--refer to datasheet for an explanation of these values`
84			`with cur_state select`
85			`tx_byte <= "00101000" when function_set,`
86			`"00000110" when entry_set,`
87			`"00001100" when set_display,`
88			`"00000001" when clr_display,`
89			`"10000000" when set_addr0,`
90			`"11000000" when set_addr1,`
91			`lcd_char when char_print0\|char_print1,`
92			`"00000000" when others;`
93
94			`--main state machine`
95			`display: process(clk, reset)`
96			`begin`
97			`if(reset='1') then`
98			`cur_state <= function_set;`
99			`elsif(clk='1' and clk'event) then`
100			`case cur_state is`
101			`--refer to intialize state machine below`
102			`when init =>`
103			`if(init_done = '1') then`
104			`cur_state <= function_set;`
105			`else`
106			`cur_state <= init;`
107			`end if;`
108
109			`--every other state but pause uses the transmit state machine`
110			`when function_set =>`
111			`if(i2 = 2000) then`
112			`cur_state <= entry_set;`
113			`else`
114			`cur_state <= function_set;`
115			`end if;`
116
117			`when entry_set =>`
118			`if(i2 = 2000) then`
119			`cur_state <= set_display;`
120			`else`
121			`cur_state <= entry_set;`
122			`end if;`
123
124			`when set_display =>`
125			`if(i2 = 2000) then`
126			`cur_state <= clr_display;`
127			`else`
128			`cur_state <= set_display;`
129			`end if;`
130
131			`when clr_display =>`
132			`i3 <= 0;`
133			`if(i2 = 2000) then`
134			`cur_state <= pause;`
135			`else`
136			`cur_state <= clr_display;`
137			`end if;`
138
139			`when pause =>`
140			`if(i3 = 82000) then`
141			`cur_state <= set_addr0;`
142			`i3 <= 0;`
143			`else`
144			`cur_state <= pause;`
145			`i3 <= i3 + 1;`
146			`end if;`
147
148			`when set_addr0 =>`
149			`if(i2 = 2000) then`
150			`cur_state <= char_print0;`
151			`lcd_addr_sig <= "00000";`
152			`else`
153			`cur_state <= set_addr0;`
154			`end if;`
155
156			`when set_addr1 =>`
157			`if(i2 = 2000) then`
158			`cur_state <= char_print1;`
159			`lcd_addr_sig <= "10000";`
160			`else`
161			`cur_state <= set_addr1;`
162			`end if;`
163
164			`when char_print0 =>`
165			`if(i2 = 2000) then`
166			`if lcd_addr_sig = "01111" then`
167			`cur_state <= set_addr1;`
168			`else`
169			`cur_state <= char_print0;`
170			`lcd_addr_sig <= lcd_addr_sig + 1;`
171			`end if;`
172			`else`
173			`cur_state <= char_print0;`
174			`end if;`
175
176			`when char_print1 =>`
177			`if(i2 = 2000) then`
178			`if lcd_addr_sig = "11111" then`
179			`cur_state <= set_addr0;`
180			`else`
181			`cur_state <= char_print1;`
182			`lcd_addr_sig <= lcd_addr_sig + 1;`
183			`end if;`
184			`else`
185			`cur_state <= char_print1;`
186			`end if;`
187
188			`when done =>`
189			`cur_state <= done;`
190			`end case;`
191			`end if;`
192			`end process display;`
193
194			`with mux select`
195			`SF_D <= SF_D0 when '0', --transmit`
196			`SF_D1 when others; --initialize`
197			`with mux select`
198			`LCD_E <= LCD_E0 when '0', --transmit`
199			`LCD_E1 when others; --initialize`
200
201			`--specified by datasheet`
202			`transmit : process(clk, reset, tx_init)`
203			`begin`
204			`if(reset='1') then`
205			`tx_state <= done;`
206			`elsif(clk='1' and clk'event) then`
207			`case tx_state is`
208			`when high_setup => --40ns`
209			`LCD_E0 <= '0';`
210			`SF_D0 <= tx_byte(7 downto 4);`
211			`if(i2 = 2) then`
212			`tx_state <= high_hold;`
213			`i2 <= 0;`
214			`else`
215			`tx_state <= high_setup;`
216			`i2 <= i2 + 1;`
217			`end if;`
218
219			`when high_hold => --230ns`
220			`LCD_E0 <= '1';`
221			`SF_D0 <= tx_byte(7 downto 4);`
222			`if(i2 = 12) then`
223			`tx_state <= oneus;`
224			`i2 <= 0;`
225			`else`
226			`tx_state <= high_hold;`
227			`i2 <= i2 + 1;`
228			`end if;`
229
230			`when oneus =>`
231			`LCD_E0 <= '0';`
232			`if(i2 = 50) then`
233			`tx_state <= low_setup;`
234			`i2 <= 0;`
235			`else`
236			`tx_state <= oneus;`
237			`i2 <= i2 + 1;`
238			`end if;`
239
240			`when low_setup =>`
241			`LCD_E0 <= '0';`
242			`SF_D0 <= tx_byte(3 downto 0);`
243			`if(i2 = 2) then`
244			`tx_state <= low_hold;`
245			`i2 <= 0;`
246			`else`
247			`tx_state <= low_setup;`
248			`i2 <= i2 + 1;`
249			`end if;`
250
251			`when low_hold =>`
252			`LCD_E0 <= '1';`
253			`SF_D0 <= tx_byte(3 downto 0);`
254			`if(i2 = 12) then`
255			`tx_state <= fortyus;`
256			`i2 <= 0;`
257			`else`
258			`tx_state <= low_hold;`
259			`i2 <= i2 + 1;`
260			`end if;`
261
262			`when fortyus =>`
263			`LCD_E0 <= '0';`
264			`if(i2 = 2000) then`
265			`tx_state <= done;`
266			`i2 <= 0;`
267			`else`
268			`tx_state <= fortyus;`
269			`i2 <= i2 + 1;`
270			`end if;`
271
272			`when done =>`
273			`LCD_E0 <= '0';`
274			`if(tx_init = '1') then`
275			`tx_state <= high_setup;`
276			`i2 <= 0;`
277			`else`
278			`tx_state <= done;`
279			`i2 <= 0;`
280			`end if;`
281
282			`end case;`
283			`end if;`
284			`end process transmit;`
285
286			`--specified by datasheet`
287			`power_on_initialize: process(clk, reset, init_init) --power on initialization sequence`
288			`begin`
289			`if(reset='1') then`
290			`init_state <= idle;`
291			`init_done <= '0';`
292			`elsif(clk='1' and clk'event) then`
293			`case init_state is`
294			`when idle =>`
295			`init_done <= '0';`
296			`if(init_init = '1') then`
297			`init_state <= fifteenms;`
298			`i <= 0;`
299			`else`
300			`init_state <= idle;`
301			`i <= i + 1;`
302			`end if;`
303
304			`when fifteenms =>`
305			`init_done <= '0';`
306			`if(i = 750000) then`
307			`init_state <= one;`
308			`i <= 0;`
309			`else`
310			`init_state <= fifteenms;`
311			`i <= i + 1;`
312			`end if;`
313
314			`when one =>`
315			`SF_D1 <= "0011";`
316			`LCD_E1 <= '1';`
317			`init_done <= '0';`
318			`if(i = 11) then`
319			`init_state<=two;`
320			`i <= 0;`
321			`else`
322			`init_state<=one;`
323			`i <= i + 1;`
324			`end if;`
325
326			`when two =>`
327			`LCD_E1 <= '0';`
328			`init_done <= '0';`
329			`if(i = 205000) then`
330			`init_state<=three;`
331			`i <= 0;`
332			`else`
333			`init_state<=two;`
334			`i <= i + 1;`
335			`end if;`
336
337			`when three =>`
338			`SF_D1 <= "0011";`
339			`LCD_E1 <= '1';`
340			`init_done <= '0';`
341			`if(i = 11) then`
342			`init_state<=four;`
343			`i <= 0;`
344			`else`
345			`init_state<=three;`
346			`i <= i + 1;`
347			`end if;`
348
349			`when four =>`
350			`LCD_E1 <= '0';`
351			`init_done <= '0';`
352			`if(i = 5000) then`
353			`init_state<=five;`
354			`i <= 0;`
355			`else`
356			`init_state<=four;`
357			`i <= i + 1;`
358			`end if;`
359
360			`when five =>`
361			`SF_D1 <= "0011";`
362			`LCD_E1 <= '1';`
363			`init_done <= '0';`
364			`if(i = 11) then`
365			`init_state<=six;`
366			`i <= 0;`
367			`else`
368			`init_state<=five;`
369			`i <= i + 1;`
370			`end if;`
371
372			`when six =>`
373			`LCD_E1 <= '0';`
374			`init_done <= '0';`
375			`if(i = 2000) then`
376			`init_state<=seven;`
377			`i <= 0;`
378			`else`
379			`init_state<=six;`
380			`i <= i + 1;`
381			`end if;`
382
383			`when seven =>`
384			`SF_D1 <= "0010";`
385			`LCD_E1 <= '1';`
386			`init_done <= '0';`
387			`if(i = 11) then`
388			`init_state<=eight;`
389			`i <= 0;`
390			`else`
391			`init_state<=seven;`
392			`i <= i + 1;`
393			`end if;`
394
395			`when eight =>`
396			`LCD_E1 <= '0';`
397			`init_done <= '0';`
398			`if(i = 2000) then`
399			`init_state<=done;`
400			`i <= 0;`
401			`else`
402			`init_state<=eight;`
403			`i <= i + 1;`
404			`end if;`
405
406			`when done =>`
407			`init_state <= done;`
408			`init_done <= '1';`
409
410			`end case;`
411
412			`end if;`
413			`end process power_on_initialize;`
414
415			`end behavior;`