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                    Core name: Xilinx LogiCORE IP Block Memory Generator
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                    Version: 4.3
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                    Release Date: September 21 2010
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================================================================================
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This document contains the following sections:
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1. Introduction
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2. New Features
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3. Supported Devices
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4. Resolved Issues
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5. Known Issues
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6. Technical Support
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7. Core Release History
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8. Legal Disclaimer
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================================================================================
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1. INTRODUCTION
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For the most recent updates to the IP installation instructions for this core,
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please go to:
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   http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
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For system requirements:
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   http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
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This file contains release notes for the Xilinx LogiCORE IP Block Memory
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Generator v4.3 solution. For the latest core updates, see the product page at:
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  http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm
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2. NEW FEATURES
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- ISE 12.3 support
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- Soft-ECC support for Virtex-6 and Spartan-6 devices
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3. SUPPORTED DEVICES
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   SPARTAN-3, SPARTAN-3 XA, SPARTAN-3E SPARTAN-3E XA, SPARTAN-3A, SPARTAN-3A XA,
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   SPARTAN-3ADSP, SPARTAN-3ADSP XA, SPARTAN-6, SPARTAN-6L, SPARTAN-6 XA
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   VIRTEX-4, VIRTEX-5, VIRTEX-6, VIRTEX-6L , QVIRTEX-6
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   QVIRTEX-4, QRVIRTEX-4, QVIRTEX-5
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4. RESOLVED ISSUES
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- Spartan-6 BRAM Memory collision error
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- Version fixed : 4.3
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  1. When the user selects SDP - in Virtex-6 devices
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      Solution: For SDP configuration, the write_mode is set as Read_First when Common Clock is enabled otherwise the write_mode is set as Write_First
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  - CR 564035
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5. KNOWN ISSUES
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   The following are known issues for v4.3 of this core at time of release:
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- Virtex-6 BRAM Memory collision error
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  1. When the user selects TDP (write_mode= Read First)
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      Impact: User will have to consider collision Issue
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- Spartan-6 BRAM Memory collision error
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  1. When the user selects TDP (write_mode= Read First)
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      Impact: User will have to consider collision Issue
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  Note: Refer to UG383, 'Conflict Avoidance' section while using TDP Memory, with
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        Write Mode = Read First in conjunction with asynchronous clocking
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- Power estimation figures in the datasheet are preliminary.
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- Core does not generate for large memories. Depending on the
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  machine the ISE CORE Generator software runs on, the maximum size of the memory that
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  can be generated will vary.  For example, a Dual Pentium-4 server
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  with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes
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  - CR 415768
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  - AR 24034
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- Out-of-range address input can cause the core to generate X's on the DOUT bus
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  - AR 23744
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- When the IP core is generated for Spartan-6 devices, the core should combine
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  two adjacent 9k BRAMs into one 18K BRAM.
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  - CR 526429
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The most recent information, including known issues, workarounds, and resolutions for
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this version is provided in the IP Release Notes User Guide located at
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     www.xilinx.com/support/documentation/user_guides/xtp025.pdf
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6. TECHNICAL SUPPORT
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To obtain technical support, create a WebCase at www.xilinx.com/support.
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Questions are routed to a team with expertise using this product.
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Xilinx provides technical support for use of this product when used
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according to the guidelines described in the core documentation, and
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cannot guarantee timing, functionality, or support of this product for
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designs that do not follow specified guidelines.
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7. CORE RELEASE HISTORY
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Date        By            Version      Description
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================================================================================
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09/21/2010  Xilinx, Inc.  4.3          ISE 12.3 support;
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07/23/2010  Xilinx, Inc.  4.2          ISE 12.2 support;
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04/19/2010  Xilinx, Inc.  4.1          ISE 12.1 support;
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03/09/2010  Xilinx, Inc.  3.3 rev 2    Fix for V6 Memory collision issue
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12/02/2009  Xilinx, Inc.  3.3 rev 1    ISE 11.4 support; Spartan-6 Low Power
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                                       Device support; Automotive Spartan 3A
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                                       DSP device support
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09/16/2009  Xilinx, Inc.  3.3          Revised to v3.3
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06/24/2009  Xilinx, Inc.  3.2          Revised to v3.2
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04/24/2009  Xilinx, Inc.  3.1          Revised to v3.1
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09/19/2008  Xilinx, Inc.  2.8          Revised to v2.8
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03/24/2008  Xilinx, Inc.  2.7          10.1 support; Revised to v2.7
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10/03/2007  Xilinx, Inc.  2.6          Revised to v2.6
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07/2007     Xilinx, Inc.  2.5          Revised to v2.5
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04/2007     Xilinx, Inc.  2.4          Revised to v2.4 rev 1
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02/2007     Xilinx, Inc.  2.4          Revised to v2.4
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11/2006     Xilinx, Inc.  2.3          Revised to v2.3
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09/2006     Xilinx, Inc.  2.2          Revised to v2.2
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06/2006     Xilinx, Inc.  2.1          Revised to v2.1
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01/2006     Xilinx, Inc.  1.1          Initial release
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================================================================================
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8. Legal Disclaimer
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(c) Copyright 2006 - 2010 Xilinx, Inc. All rights reserved.
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This file contains confidential and proprietary information
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of Xilinx, Inc. and is protected under U.S. and
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international copyright and other intellectual property
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laws.
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DISCLAIMER
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This disclaimer is not a license and does not grant any
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rights to the materials distributed herewith. Except as
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otherwise provided in a valid license issued to you by
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Xilinx, and to the maximum extent permitted by applicable
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law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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(2) Xilinx shall not be liable (whether in contract or tort,
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including negligence, or under any other theory of
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liability) for any loss or damage of any kind or nature
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related to, arising under or in connection with these
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materials, including for any direct, or any indirect,
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special, incidental, or consequential loss or damage
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(including loss of data, profits, goodwill, or any type of
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loss or damage suffered as a result of any action brought
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by a third party) even if such damage or loss was
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reasonably foreseeable or Xilinx had been advised of the
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possibility of the same.
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CRITICAL APPLICATIONS
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Xilinx products are not designed or intended to be fail-
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safe, or for use in any application requiring fail-safe
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performance, such as life-support or safety devices or
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systems, Class III medical devices, nuclear facilities,
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applications related to the deployment of airbags, or any
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other applications that could lead to death, personal
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injury, or severe property or environmental damage
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(individually and collectively, "Critical
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Applications"). Customer assumes the sole risk and
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liability of any use of Xilinx products in Critical
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Applications, subject only to applicable laws and
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regulations governing limitations on product liability.
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THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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PART OF THIS FILE AT ALL TIMES.
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