URL https://opencores.org/ocsvn/z80soc/z80soc/trunk

Subversion Repositories z80soc

[/] [z80soc/] [trunk/] [V0.7.1a/] [S3E/] [memoryCores/] [rom.cgc] - Blame information for rev 42

Details | Compare with Previous | View Log




   xilinx.com
   project
   rom
   1.0
   
      
         charram2k
         
         
         
         
            false
            2048
            WRITE_FIRST
            READ_FIRST
            8
            8
            false
            false
            8kx2
            True_Dual_Port_RAM
            false
            9
            false
            false
            0
            false
            0
            false
            false
            false
            Always_Enabled
            Always_Enabled
            false
            false
            false
            false
            Minimum_Area
            false
            false
            8
            8
            SYNC
            false
            0
            0
            true
            false
            F:\FPGA\Z80SoC\V0.7\rom\char.coe
            Single_Bit_Error_Injection
            ALL
            CE
            CE
         
         
            
             
               coregen
               ./
               ./tmp/
               ./tmp/_cg
             
             
               xc3s500e
               spartan3e
               fg320
               -4
             
             
               BusFormatAngleBracketNotRipped
               VHDL
               true
               Other
               false
               false
               false
               Ngc
               false
             
             
               Behavioral
               VHDL
               false
             
           
         
      
      
         lcdvram
         
         
         
         
            false
            32
            READ_FIRST
            READ_FIRST
            8
            8
            false
            false
            8kx2
            Simple_Dual_Port_RAM
            false
            9
            false
            false
            0
            false
            0
            false
            false
            false
            Always_Enabled
            Always_Enabled
            false
            false
            false
            false
            Minimum_Area
            false
            false
            8
            8
            SYNC
            false
            0
            0
            false
            false
            no_coe_file_loaded
            Single_Bit_Error_Injection
            ALL
            CE
            CE
         
         
            
             
               coregen
               ./
               ./tmp/
               ./tmp/_cg
             
             
               xc3s500e
               spartan3e
               fg320
               -4
             
             
               BusFormatAngleBracketNotRipped
               VHDL
               true
               Other
               false
               false
               false
               Ngc
               false
             
             
               Behavioral
               VHDL
               false
             
           
         
      
      
         ram
         
         
         
         
            50
            false
            12288
            false
            WRITE_FIRST
            WRITE_FIRST
            false
            false
            8
            8
            false
            false
            8kx2
            Single_Port_RAM
            false
            9
            false
            0
            false
            0
            false
            false
            false
            Always_Enabled
            Always_Enabled
            100
            false
            false
            false
            false
            50
            Minimum_Area
            false
            No_ECC
            100
            false
            100
            8
            8
            SYNC
            false
            false
            100
            0
            0
            false
            false
            no_coe_file_loaded
            Single_Bit_Error_Injection
            ALL
            CE
            CE
         
         
            
             
               coregen
               ./
               ./tmp/
               ./tmp/_cg
             
             
               xc3s500e
               spartan3e
               fg320
               -4
             
             
               BusFormatAngleBracketNotRipped
               VHDL
               false
               Other
               false
               false
               false
               Ngc
               false
             
             
               Behavioral
               VHDL
               false
             
           
         
      
      
         ram24k
         
         
         
         
            50
            false
            24576
            false
            WRITE_FIRST
            WRITE_FIRST
            false
            false
            8
            8
            false
            false
            8kx2
            Single_Port_RAM
            false
            9
            false
            0
            false
            0
            false
            false
            false
            Always_Enabled
            Always_Enabled
            100
            false
            false
            false
            false
            50
            Minimum_Area
            false
            No_ECC
            100
            false
            100
            8
            8
            SYNC
            false
            false
            100
            0
            0
            false
            false
            no_coe_file_loaded
            Single_Bit_Error_Injection
            ALL
            CE
            CE
         
         
            
             
               coregen
               ./
               ./tmp/
               ./tmp/_cg
             
             
               xc3s500e
               spartan3e
               fg320
               -4
             
             
               BusFormatAngleBracketNotRipped
               VHDL
               false
               Other
               false
               false
               false
               Ngc
               false
             
             
               Behavioral
               VHDL
               false
             
           
         
      
      
         ram32k
         
         
         
         
            false
            32768
            WRITE_FIRST
            WRITE_FIRST
            8
            8
            false
            false
            8kx2
            Single_Port_RAM
            false
            9
            false
            false
            0
            false
            0
            false
            false
            false
            Always_Enabled
            Always_Enabled
            false
            false
            false
            false
            Minimum_Area
            false
            false
            8
            8
            SYNC
            false
            0
            0
            false
            false
            no_coe_file_loaded
            Single_Bit_Error_Injection
            ALL
            CE
            CE
         
         
            
             
               coregen
               ./
               ./tmp/
               ./tmp/_cg
             
             
               xc3s500e
               spartan3e
               fg320
               -4
             
             
               BusFormatAngleBracketNotRipped
               VHDL
               true
               Other
               false
               false
               false
               Ngc
               false
             
             
               Behavioral
               VHDL
               false
             
           
         
      
      
         ram8k
         
         
         
         
            50
            false
            8192
            false
            WRITE_FIRST
            WRITE_FIRST
            false
            false
            8
            8
            false
            false
            8kx2
            Single_Port_RAM
            false
            9
            false
            0
            false
            0
            false
            false
            false
            Always_Enabled
            Always_Enabled
            100
            false
            false
            false
            false
            50
            Minimum_Area
            false
            No_ECC
            100
            false
            100
            8
            8
            SYNC
            false
            false
            100
            0
            0
            false
            false
            no_coe_file_loaded
            Single_Bit_Error_Injection
            ALL
            CE
            CE
         
         
            
             
               coregen
               ./
               ./tmp/
               ./tmp/_cg
             
             
               xc3s500e
               spartan3e
               fg320
               -4
             
             
               BusFormatAngleBracketNotRipped
               VHDL
               false
               Other
               false
               false
               false
               Ngc
               false
             
             
               Behavioral
               VHDL
               false
             
           
         
      
      
         rom
         
         
         
         
            0
            false
            16384
            false
            WRITE_FIRST
            WRITE_FIRST
            false
            false
            8
            8
            false
            false
            8kx2
            Single_Port_ROM
            false
            9
            false
            0
            false
            0
            false
            false
            false
            Always_Enabled
            Always_Enabled
            100
            false
            false
            false
            false
            0
            Minimum_Area
            false
            No_ECC
            0
            false
            100
            8
            8
            SYNC
            false
            false
            0
            0
            0
            true
            false
            .\rom.coe
            Single_Bit_Error_Injection
            ALL
            CE
            CE
         
         
            
             
               coregen
               ./
               ./tmp/
               ./tmp/_cg
             
             
               xc3s500e
               spartan3e
               fg320
               -4
             
             
               BusFormatAngleBracketNotRipped
               VHDL
               true
               Other
               false
               false
               false
               Ngc
               false
             
             
               Behavioral
               VHDL
               false
             
           
            
               
                  customization_generator
                  
                     ./rom.mif
                     mif
                     Tue Nov 23 01:46:24 GMT 2010
                     0x63443647
                  
               
               
                  ip_xco_generator
                  
                     ./rom.xco
                     xco
                     Tue Nov 23 01:46:25 GMT 2010
                     0xB71F7453
                  
               
               
                  implementation_netlist_generator
                  
                     ./blk_mem_gen_ds512.pdf
                     pdf
                     Tue Nov 23 01:48:12 GMT 2010
                     0xFF542E99
                  
                  
                     ./blk_mem_gen_readme.txt
                     txt
                     Tue Nov 23 01:48:12 GMT 2010
                     0xED96AB8B
                  
                  
                     ./rom.asy
                     asy
                     Tue Nov 23 01:46:50 GMT 2010
                     0x5F2CE6A2
                  
                  
                     ./rom.mif
                     mif
                     Tue Nov 23 01:46:50 GMT 2010
                     0x63443647
                  
                  
                     ./rom.ngc
                     ngc
                     Tue Nov 23 01:48:30 GMT 2010
                     0xE2BDD044
                  
                  
                     ./rom.vhd
                     vhdl
                     Tue Nov 23 01:48:12 GMT 2010
                     0x72FF60B5
                  
                  
                     ./rom.vho
                     vho
                     Tue Nov 23 01:48:12 GMT 2010
                     0x70F4DC96
                  
               
               
                  instantiation_template_generator
                  
                     ./rom.vho
                     vho
                     Tue Nov 23 01:48:32 GMT 2010
                     0x70F4DC96
                  
               
               
                  xco_generator
                  
                     ./rom.xco
                     xco
                     Tue Nov 23 01:48:37 GMT 2010
                     0x099A1BBB
                  
               
               
                  xmdf_generator
                  
                     ./rom_xmdf.tcl
                     tclXmdf
                     tcl
                     Tue Nov 23 01:48:37 GMT 2010
                     0x76D4483B
                  
               
               
                  ise_generator
                  
                     ./_xmsgs/pn_parser.xmsgs
                     ignore
                     unknown
                     Tue Nov 23 01:48:45 GMT 2010
                     0x4CFB085B
                  
                  
                     ./rom.gise
                     ignore
                     gise
                     Tue Nov 23 01:48:46 GMT 2010
                     0x88C91CE0
                  
                  
                     ./rom.xise
                     ignore
                     xise
                     Tue Nov 23 01:48:46 GMT 2010
                     0x801EEE48
                  
               
               
                  deliver_readme_generator
               
               
                  flist_generator
                  
                     ./rom_flist.txt
                     ignore
                     txtFlist
                     txt
                     Tue Nov 23 01:48:46 GMT 2010
                     0xF98FFE6A
                  
               
               
                  view_readme_generator
               
            
         
      
      
         rom8k
         
         
         
         
            0
            false
            8192
            false
            WRITE_FIRST
            WRITE_FIRST
            false
            false
            8
            8
            false
            false
            8kx2
            Single_Port_ROM
            false
            9
            false
            0
            false
            0
            false
            false
            false
            Always_Enabled
            Always_Enabled
            100
            false
            false
            false
            false
            0
            Minimum_Area
            false
            No_ECC
            0
            false
            100
            8
            8
            SYNC
            false
            false
            0
            0
            0
            true
            false
            E:\FPGA Projetos\Z80SoC\V0.7.1\rom\rom8k.coe
            Single_Bit_Error_Injection
            ALL
            CE
            CE
         
         
            
             
               coregen
               ./
               ./tmp/
               ./tmp/_cg
             
             
               xc3s500e
               spartan3e
               fg320
               -4
             
             
               BusFormatAngleBracketNotRipped
               VHDL
               true
               Other
               false
               false
               false
               Ngc
               false
             
             
               Behavioral
               VHDL
               false
             
           
         
      
      
         vram
         
         
         
         
            50
            false
            6143
            false
            WRITE_FIRST
            WRITE_FIRST
            false
            false
            8
            8
            false
            false
            8kx2
            True_Dual_Port_RAM
            false
            9
            false
            0
            false
            0
            false
            false
            false
            Always_Enabled
            Always_Enabled
            100
            false
            false
            false
            false
            50
            Minimum_Area
            false
            No_ECC
            100
            false
            100
            8
            8
            SYNC
            false
            false
            100
            0
            0
            false
            false
            no_coe_file_loaded
            Single_Bit_Error_Injection
            ALL
            CE
            CE
         
         
            
             
               coregen
               ./
               ./tmp/
               ./tmp/_cg
             
             
               xc3s500e
               spartan3e
               fg320
               -4
             
             
               BusFormatAngleBracketNotRipped
               VHDL
               true
               Other
               false
               false
               false
               Ngc
               false
             
             
               Behavioral
               VHDL
               false
             
           
         
      
      
         vram3200x8
         
         
         
         
            50
            false
            3200
            false
            WRITE_FIRST
            WRITE_FIRST
            false
            false
            8
            8
            false
            false
            8kx2
            True_Dual_Port_RAM
            false
            9
            false
            0
            false
            0
            false
            false
            false
            Always_Enabled
            Always_Enabled
            100
            false
            false
            false
            false
            50
            Minimum_Area
            false
            No_ECC
            100
            false
            100
            8
            8
            SYNC
            false
            false
            100
            0
            0
            false
            false
            no_coe_file_loaded
            Single_Bit_Error_Injection
            ALL
            CE
            CE
         
         
            
             
               coregen
               ./
               ./tmp/
               ./tmp/_cg
             
             
               xc3s500e
               spartan3e
               fg320
               -4
             
             
               BusFormatAngleBracketNotRipped
               VHDL
               true
               Other
               false
               false
               false
               Ngc
               false
             
             
               Behavioral
               VHDL
               false
             
           
         
      
   
   
   
      
       
         rom
         ./
         ./tmp/
         ./tmp/_cg
       
       
         xc3s500e
         spartan3e
         fg320
         -4
       
       
         BusFormatAngleBracketNotRipped
         VHDL
         false
         Other
         false
         false
         false
         Ngc
         false
       
       
         Behavioral
         VHDL
         false
       
     
   


Browse

Tools

Subversion Repositories z80soc

[/] [z80soc/] [trunk/] [V0.7.1a/] [S3E/] [memoryCores/] [rom.cgc] - Blame information for rev 42

Line No.	Rev	Author	Line
1	41	rrred
2
3			`xilinx.com`
4			`project`
5			`rom`
6			`1.0`
7
8
9			`charram2k`
10
11
12
13
14			`false`
15			`2048`
16			`WRITE_FIRST`
17			`READ_FIRST`
18			`8`
19			`8`
20			`false`
21			`false`
22			`8kx2`
23			`True_Dual_Port_RAM`
24			`false`
25			`9`
26			`false`
27			`false`
28			`0`
29			`false`
30			`0`
31			`false`
32			`false`
33			`false`
34			`Always_Enabled`
35			`Always_Enabled`
36			`false`
37			`false`
38			`false`
39			`false`
40			`Minimum_Area`
41			`false`
42			`false`
43			`8`
44			`8`
45			`SYNC`
46			`false`
47			`0`
48			`0`
49			`true`
50			`false`
51			`F:\FPGA\Z80SoC\V0.7\rom\char.coe`
52			`Single_Bit_Error_Injection`
53			`ALL`
54			`CE`
55			`CE`
56
57
58
59
60			`coregen`
61			`./`
62			`./tmp/`
63			`./tmp/_cg`
64
65
66			`xc3s500e`
67			`spartan3e`
68			`fg320`
69			`-4`
70
71
72			`BusFormatAngleBracketNotRipped`
73			`VHDL`
74			`true`
75			`Other`
76			`false`
77			`false`
78			`false`
79			`Ngc`
80			`false`
81
82
83			`Behavioral`
84			`VHDL`
85			`false`
86
87
88
89
90
91			`lcdvram`
92
93
94
95
96			`false`
97			`32`
98			`READ_FIRST`
99			`READ_FIRST`
100			`8`
101			`8`
102			`false`
103			`false`
104			`8kx2`
105			`Simple_Dual_Port_RAM`
106			`false`
107			`9`
108			`false`
109			`false`
110			`0`
111			`false`
112			`0`
113			`false`
114			`false`
115			`false`
116			`Always_Enabled`
117			`Always_Enabled`
118			`false`
119			`false`
120			`false`
121			`false`
122			`Minimum_Area`
123			`false`
124			`false`
125			`8`
126			`8`
127			`SYNC`
128			`false`
129			`0`
130			`0`
131			`false`
132			`false`
133			`no_coe_file_loaded`
134			`Single_Bit_Error_Injection`
135			`ALL`
136			`CE`
137			`CE`
138
139
140
141
142			`coregen`
143			`./`
144			`./tmp/`
145			`./tmp/_cg`
146
147
148			`xc3s500e`
149			`spartan3e`
150			`fg320`
151			`-4`
152
153
154			`BusFormatAngleBracketNotRipped`
155			`VHDL`
156			`true`
157			`Other`
158			`false`
159			`false`
160			`false`
161			`Ngc`
162			`false`
163
164
165			`Behavioral`
166			`VHDL`
167			`false`
168
169
170
171
172
173			`ram`
174
175
176
177
178			`50`
179			`false`
180			`12288`
181			`false`
182			`WRITE_FIRST`
183			`WRITE_FIRST`
184			`false`
185			`false`
186			`8`
187			`8`
188			`false`
189			`false`
190			`8kx2`
191			`Single_Port_RAM`
192			`false`
193			`9`
194			`false`
195			`0`
196			`false`
197			`0`
198			`false`
199			`false`
200			`false`
201			`Always_Enabled`
202			`Always_Enabled`
203			`100`
204			`false`
205			`false`
206			`false`
207			`false`
208			`50`
209			`Minimum_Area`
210			`false`
211			`No_ECC`
212			`100`
213			`false`
214			`100`
215			`8`
216			`8`
217			`SYNC`
218			`false`
219			`false`
220			`100`
221			`0`
222			`0`
223			`false`
224			`false`
225			`no_coe_file_loaded`
226			`Single_Bit_Error_Injection`
227			`ALL`
228			`CE`
229			`CE`
230
231
232
233
234			`coregen`
235			`./`
236			`./tmp/`
237			`./tmp/_cg`
238
239
240			`xc3s500e`
241			`spartan3e`
242			`fg320`
243			`-4`
244
245
246			`BusFormatAngleBracketNotRipped`
247			`VHDL`
248			`false`
249			`Other`
250			`false`
251			`false`
252			`false`
253			`Ngc`
254			`false`
255
256
257			`Behavioral`
258			`VHDL`
259			`false`
260
261
262
263
264
265			`ram24k`
266
267
268
269
270			`50`
271			`false`
272			`24576`
273			`false`
274			`WRITE_FIRST`
275			`WRITE_FIRST`
276			`false`
277			`false`
278			`8`
279			`8`
280			`false`
281			`false`
282			`8kx2`
283			`Single_Port_RAM`
284			`false`
285			`9`
286			`false`
287			`0`
288			`false`
289			`0`
290			`false`
291			`false`
292			`false`
293			`Always_Enabled`
294			`Always_Enabled`
295			`100`
296			`false`
297			`false`
298			`false`
299			`false`
300			`50`
301			`Minimum_Area`
302			`false`
303			`No_ECC`
304			`100`
305			`false`
306			`100`
307			`8`
308			`8`
309			`SYNC`
310			`false`
311			`false`
312			`100`
313			`0`
314			`0`
315			`false`
316			`false`
317			`no_coe_file_loaded`
318			`Single_Bit_Error_Injection`
319			`ALL`
320			`CE`
321			`CE`
322
323
324
325
326			`coregen`
327			`./`
328			`./tmp/`
329			`./tmp/_cg`
330
331
332			`xc3s500e`
333			`spartan3e`
334			`fg320`
335			`-4`
336
337
338			`BusFormatAngleBracketNotRipped`
339			`VHDL`
340			`false`
341			`Other`
342			`false`
343			`false`
344			`false`
345			`Ngc`
346			`false`
347
348
349			`Behavioral`
350			`VHDL`
351			`false`
352
353
354
355
356
357			`ram32k`
358
359
360
361
362			`false`
363			`32768`
364			`WRITE_FIRST`
365			`WRITE_FIRST`
366			`8`
367			`8`
368			`false`
369			`false`
370			`8kx2`
371			`Single_Port_RAM`
372			`false`
373			`9`
374			`false`
375			`false`
376			`0`
377			`false`
378			`0`
379			`false`
380			`false`
381			`false`
382			`Always_Enabled`
383			`Always_Enabled`
384			`false`
385			`false`
386			`false`
387			`false`
388			`Minimum_Area`
389			`false`
390			`false`
391			`8`
392			`8`
393			`SYNC`
394			`false`
395			`0`
396			`0`
397			`false`
398			`false`
399			`no_coe_file_loaded`
400			`Single_Bit_Error_Injection`
401			`ALL`
402			`CE`
403			`CE`
404
405
406
407
408			`coregen`
409			`./`
410			`./tmp/`
411			`./tmp/_cg`
412
413
414			`xc3s500e`
415			`spartan3e`
416			`fg320`
417			`-4`
418
419
420			`BusFormatAngleBracketNotRipped`
421			`VHDL`
422			`true`
423			`Other`
424			`false`
425			`false`
426			`false`
427			`Ngc`
428			`false`
429
430
431			`Behavioral`
432			`VHDL`
433			`false`
434
435
436
437
438
439			`ram8k`
440
441
442
443
444			`50`
445			`false`
446			`8192`
447			`false`
448			`WRITE_FIRST`
449			`WRITE_FIRST`
450			`false`
451			`false`
452			`8`
453			`8`
454			`false`
455			`false`
456			`8kx2`
457			`Single_Port_RAM`
458			`false`
459			`9`
460			`false`
461			`0`
462			`false`
463			`0`
464			`false`
465			`false`
466			`false`
467			`Always_Enabled`
468			`Always_Enabled`
469			`100`
470			`false`
471			`false`
472			`false`
473			`false`
474			`50`
475			`Minimum_Area`
476			`false`
477			`No_ECC`
478			`100`
479			`false`
480			`100`
481			`8`
482			`8`
483			`SYNC`
484			`false`
485			`false`
486			`100`
487			`0`
488			`0`
489			`false`
490			`false`
491			`no_coe_file_loaded`
492			`Single_Bit_Error_Injection`
493			`ALL`
494			`CE`
495			`CE`
496
497
498
499
500			`coregen`
501			`./`
502			`./tmp/`
503			`./tmp/_cg`
504
505
506			`xc3s500e`
507			`spartan3e`
508			`fg320`
509			`-4`
510
511
512			`BusFormatAngleBracketNotRipped`
513			`VHDL`
514			`false`
515			`Other`
516			`false`
517			`false`
518			`false`
519			`Ngc`
520			`false`
521
522
523			`Behavioral`
524			`VHDL`
525			`false`
526
527
528
529
530
531			`rom`
532
533
534
535
536			`0`
537			`false`
538			`16384`
539			`false`
540			`WRITE_FIRST`
541			`WRITE_FIRST`
542			`false`
543			`false`
544			`8`
545			`8`
546			`false`
547			`false`
548			`8kx2`
549			`Single_Port_ROM`
550			`false`
551			`9`
552			`false`
553			`0`
554			`false`
555			`0`
556			`false`
557			`false`
558			`false`
559			`Always_Enabled`
560			`Always_Enabled`
561			`100`
562			`false`
563			`false`
564			`false`
565			`false`
566			`0`
567			`Minimum_Area`
568			`false`
569			`No_ECC`
570			`0`
571			`false`
572			`100`
573			`8`
574			`8`
575			`SYNC`
576			`false`
577			`false`
578			`0`
579			`0`
580			`0`
581			`true`
582			`false`
583			`.\rom.coe`
584			`Single_Bit_Error_Injection`
585			`ALL`
586			`CE`
587			`CE`
588
589
590
591
592			`coregen`
593			`./`
594			`./tmp/`
595			`./tmp/_cg`
596
597
598			`xc3s500e`
599			`spartan3e`
600			`fg320`
601			`-4`
602
603
604			`BusFormatAngleBracketNotRipped`
605			`VHDL`
606			`true`
607			`Other`
608			`false`
609			`false`
610			`false`
611			`Ngc`
612			`false`
613
614
615			`Behavioral`
616			`VHDL`
617			`false`
618
619
620
621
622			`customization_generator`
623
624			`./rom.mif`
625			`mif`
626			`Tue Nov 23 01:46:24 GMT 2010`
627			`0x63443647`
628
629
630
631			`ip_xco_generator`
632
633			`./rom.xco`
634			`xco`
635			`Tue Nov 23 01:46:25 GMT 2010`
636			`0xB71F7453`
637
638
639
640			`implementation_netlist_generator`
641
642			`./blk_mem_gen_ds512.pdf`
643			`pdf`
644			`Tue Nov 23 01:48:12 GMT 2010`
645			`0xFF542E99`
646
647
648			`./blk_mem_gen_readme.txt`
649			`txt`
650			`Tue Nov 23 01:48:12 GMT 2010`
651			`0xED96AB8B`
652
653
654			`./rom.asy`
655			`asy`
656			`Tue Nov 23 01:46:50 GMT 2010`
657			`0x5F2CE6A2`
658
659
660			`./rom.mif`
661			`mif`
662			`Tue Nov 23 01:46:50 GMT 2010`
663			`0x63443647`
664
665
666			`./rom.ngc`
667			`ngc`
668			`Tue Nov 23 01:48:30 GMT 2010`
669			`0xE2BDD044`
670
671
672			`./rom.vhd`
673			`vhdl`
674			`Tue Nov 23 01:48:12 GMT 2010`
675			`0x72FF60B5`
676
677
678			`./rom.vho`
679			`vho`
680			`Tue Nov 23 01:48:12 GMT 2010`
681			`0x70F4DC96`
682
683
684
685			`instantiation_template_generator`
686
687			`./rom.vho`
688			`vho`
689			`Tue Nov 23 01:48:32 GMT 2010`
690			`0x70F4DC96`
691
692
693
694			`xco_generator`
695
696			`./rom.xco`
697			`xco`
698			`Tue Nov 23 01:48:37 GMT 2010`
699			`0x099A1BBB`
700
701
702
703			`xmdf_generator`
704
705			`./rom_xmdf.tcl`
706			`tclXmdf`
707			`tcl`
708			`Tue Nov 23 01:48:37 GMT 2010`
709			`0x76D4483B`
710
711
712
713			`ise_generator`
714
715			`./_xmsgs/pn_parser.xmsgs`
716			`ignore`
717			`unknown`
718			`Tue Nov 23 01:48:45 GMT 2010`
719			`0x4CFB085B`
720
721
722			`./rom.gise`
723			`ignore`
724			`gise`
725			`Tue Nov 23 01:48:46 GMT 2010`
726			`0x88C91CE0`
727
728
729			`./rom.xise`
730			`ignore`
731			`xise`
732			`Tue Nov 23 01:48:46 GMT 2010`
733			`0x801EEE48`
734
735
736
737			`deliver_readme_generator`
738
739
740			`flist_generator`
741
742			`./rom_flist.txt`
743			`ignore`
744			`txtFlist`
745			`txt`
746			`Tue Nov 23 01:48:46 GMT 2010`
747			`0xF98FFE6A`
748
749
750
751			`view_readme_generator`
752
753
754
755
756
757			`rom8k`
758
759
760
761
762			`0`
763			`false`
764			`8192`
765			`false`
766			`WRITE_FIRST`
767			`WRITE_FIRST`
768			`false`
769			`false`
770			`8`
771			`8`
772			`false`
773			`false`
774			`8kx2`
775			`Single_Port_ROM`
776			`false`
777			`9`
778			`false`
779			`0`
780			`false`
781			`0`
782			`false`
783			`false`
784			`false`
785			`Always_Enabled`
786			`Always_Enabled`
787			`100`
788			`false`
789			`false`
790			`false`
791			`false`
792			`0`
793			`Minimum_Area`
794			`false`
795			`No_ECC`
796			`0`
797			`false`
798			`100`
799			`8`
800			`8`
801			`SYNC`
802			`false`
803			`false`
804			`0`
805			`0`
806			`0`
807			`true`
808			`false`
809			`E:\FPGA Projetos\Z80SoC\V0.7.1\rom\rom8k.coe`
810			`Single_Bit_Error_Injection`
811			`ALL`
812			`CE`
813			`CE`
814
815
816
817
818			`coregen`
819			`./`
820			`./tmp/`
821			`./tmp/_cg`
822
823
824			`xc3s500e`
825			`spartan3e`
826			`fg320`
827			`-4`
828
829
830			`BusFormatAngleBracketNotRipped`
831			`VHDL`
832			`true`
833			`Other`
834			`false`
835			`false`
836			`false`
837			`Ngc`
838			`false`
839
840
841			`Behavioral`
842			`VHDL`
843			`false`
844
845
846
847
848
849			`vram`
850
851
852
853
854			`50`
855			`false`
856			`6143`
857			`false`
858			`WRITE_FIRST`
859			`WRITE_FIRST`
860			`false`
861			`false`
862			`8`
863			`8`
864			`false`
865			`false`
866			`8kx2`
867			`True_Dual_Port_RAM`
868			`false`
869			`9`
870			`false`
871			`0`
872			`false`
873			`0`
874			`false`
875			`false`
876			`false`
877			`Always_Enabled`
878			`Always_Enabled`
879			`100`
880			`false`
881			`false`
882			`false`
883			`false`
884			`50`
885			`Minimum_Area`
886			`false`
887			`No_ECC`
888			`100`
889			`false`
890			`100`
891			`8`
892			`8`
893			`SYNC`
894			`false`
895			`false`
896			`100`
897			`0`
898			`0`
899			`false`
900			`false`
901			`no_coe_file_loaded`
902			`Single_Bit_Error_Injection`
903			`ALL`
904			`CE`
905			`CE`
906
907
908
909
910			`coregen`
911			`./`
912			`./tmp/`
913			`./tmp/_cg`
914
915
916			`xc3s500e`
917			`spartan3e`
918			`fg320`
919			`-4`
920
921
922			`BusFormatAngleBracketNotRipped`
923			`VHDL`
924			`true`
925			`Other`
926			`false`
927			`false`
928			`false`
929			`Ngc`
930			`false`
931
932
933			`Behavioral`
934			`VHDL`
935			`false`
936
937
938
939
940
941			`vram3200x8`
942
943
944
945
946			`50`
947			`false`
948			`3200`
949			`false`
950			`WRITE_FIRST`
951			`WRITE_FIRST`
952			`false`
953			`false`
954			`8`
955			`8`
956			`false`
957			`false`
958			`8kx2`
959			`True_Dual_Port_RAM`
960			`false`
961			`9`
962			`false`
963			`0`
964			`false`
965			`0`
966			`false`
967			`false`
968			`false`
969			`Always_Enabled`
970			`Always_Enabled`
971			`100`
972			`false`
973			`false`
974			`false`
975			`false`
976			`50`
977			`Minimum_Area`
978			`false`
979			`No_ECC`
980			`100`
981			`false`
982			`100`
983			`8`
984			`8`
985			`SYNC`
986			`false`
987			`false`
988			`100`
989			`0`
990			`0`
991			`false`
992			`false`
993			`no_coe_file_loaded`
994			`Single_Bit_Error_Injection`
995			`ALL`
996			`CE`
997			`CE`
998
999
1000
1001
1002			`coregen`
1003			`./`
1004			`./tmp/`
1005			`./tmp/_cg`
1006
1007
1008			`xc3s500e`
1009			`spartan3e`
1010			`fg320`
1011			`-4`
1012
1013
1014			`BusFormatAngleBracketNotRipped`
1015			`VHDL`
1016			`true`
1017			`Other`
1018			`false`
1019			`false`
1020			`false`
1021			`Ngc`
1022			`false`
1023
1024
1025			`Behavioral`
1026			`VHDL`
1027			`false`
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037			`rom`
1038			`./`
1039			`./tmp/`
1040			`./tmp/_cg`
1041
1042
1043			`xc3s500e`
1044			`spartan3e`
1045			`fg320`
1046			`-4`
1047
1048
1049			`BusFormatAngleBracketNotRipped`
1050			`VHDL`
1051			`false`
1052			`Other`
1053			`false`
1054			`false`
1055			`false`
1056			`Ngc`
1057			`false`
1058
1059
1060			`Behavioral`
1061			`VHDL`
1062			`false`
1063
1064
1065
1066