URL
https://opencores.org/ocsvn/z80soc/z80soc/trunk
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Welcome to Xilinx CORE Generator.
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Help system initialized.
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Wrote file for project 'rom'.
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Wrote file for project 'rom'.
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Customize and Generate
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Customizing IP...
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Release 12.3 - Xilinx CORE Generator IP GUI Launcher M.70d (nt)
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Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
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Initializing IP model...
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Finished initialising IP model.
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Finished Customizing.
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Generating IP...
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XST: HDL Compilation
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XST: Design Hierarchy Analysis
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XST: HDL Analysis
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XST: HDL Synthesis
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XST: Advanced HDL Synthesis
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XST: Low Level Synthesis
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Generating Implementation files.
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Generating NGC file.
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Finished Generation Stage.
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Generating IP instantiation template...
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Generating the VHDL instantiation template.
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Finished generating IP instantiation template.
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Generating metadata file...
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Finished generating metadata file.
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Generating metadata file...
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Finished generating metadata file.
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Generating ISE file...
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Finished ISE file generation.
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Generating FLIST file...
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Finished FLIST file generation.
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Preparing output directory...
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Finished preparing output directory.
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Launching readme viewer...
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Launched readme viewer.
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Moving files to output directory...
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Finished moving files to output directory
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Saved options for project 'rom'.
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View Readme File
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Launching readme viewer...
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Launched readme viewer.
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