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--     This file is owned and controlled by Xilinx and must be used           --

--     solely for design, simulation, implementation and creation of          --

--     design files limited to Xilinx devices or technologies. Use            --

--     with non-Xilinx devices or technologies is expressly prohibited        --

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-- The following code must appear in the VHDL architecture header:

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG

component rom

        port (

        clka: IN std_logic;

        addra: IN std_logic_VECTOR(13 downto 0);

        douta: OUT std_logic_VECTOR(7 downto 0));

end component;

-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture

-- body. Substitute your own instance name and net names.

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG

your_instance_name : rom

                port map (

                        clka => clka,

                        addra => addra,

                        douta => douta);

-- INST_TAG_END ------ End INSTANTIATION Template ------------

-- You must compile the wrapper file rom.vhd when simulating

-- the core, rom. When compiling the wrapper file, be sure to

-- reference the XilinxCoreLib VHDL simulation library. For detailed

-- instructions, please refer to the "CORE Generator Help".