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[/] [z80soc/] [trunk/] [V0.7.1a/] [S3E/] [memoryCores/] [vram.vhd] - Blame information for rev 42

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1 41 rrred
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--     This file is owned and controlled by Xilinx and must be used           --
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--     solely for design, simulation, implementation and creation of          --
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--     design files limited to Xilinx devices or technologies. Use            --
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--     with non-Xilinx devices or technologies is expressly prohibited        --
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--     and immediately terminates your license.                               --
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--                                                                            --
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--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
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--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
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--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
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--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
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--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
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--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
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--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
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--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
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--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
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--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
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--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
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--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
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--     FOR A PARTICULAR PURPOSE.                                              --
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--                                                                            --
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--     Xilinx products are not intended for use in life support               --
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--     appliances, devices, or systems. Use in such applications are          --
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--     expressly prohibited.                                                  --
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--                                                                            --
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--     (c) Copyright 1995-2009 Xilinx, Inc.                                   --
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--     All rights reserved.                                                   --
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--------------------------------------------------------------------------------
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-- You must compile the wrapper file vram.vhd when simulating
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-- the core, vram. When compiling the wrapper file, be sure to
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-- reference the XilinxCoreLib VHDL simulation library. For detailed
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-- instructions, please refer to the "CORE Generator Help".
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-- The synthesis directives "translate_off/translate_on" specified
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-- below are supported by Xilinx, Mentor Graphics and Synplicity
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-- synthesis tools. Ensure they are correct for your synthesis tool(s).
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- synthesis translate_off
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Library XilinxCoreLib;
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-- synthesis translate_on
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ENTITY vram IS
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        port (
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        clka: IN std_logic;
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        wea: IN std_logic_VECTOR(0 downto 0);
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        addra: IN std_logic_VECTOR(12 downto 0);
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        dina: IN std_logic_VECTOR(7 downto 0);
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        douta: OUT std_logic_VECTOR(7 downto 0);
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        clkb: IN std_logic;
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        web: IN std_logic_VECTOR(0 downto 0);
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        addrb: IN std_logic_VECTOR(12 downto 0);
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        dinb: IN std_logic_VECTOR(7 downto 0);
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        doutb: OUT std_logic_VECTOR(7 downto 0));
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END vram;
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ARCHITECTURE vram_a OF vram IS
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-- synthesis translate_off
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component wrapped_vram
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        port (
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        clka: IN std_logic;
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        wea: IN std_logic_VECTOR(0 downto 0);
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        addra: IN std_logic_VECTOR(12 downto 0);
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        dina: IN std_logic_VECTOR(7 downto 0);
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        douta: OUT std_logic_VECTOR(7 downto 0);
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        clkb: IN std_logic;
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        web: IN std_logic_VECTOR(0 downto 0);
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        addrb: IN std_logic_VECTOR(12 downto 0);
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        dinb: IN std_logic_VECTOR(7 downto 0);
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        doutb: OUT std_logic_VECTOR(7 downto 0));
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end component;
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-- Configuration specification 
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        for all : wrapped_vram use entity XilinxCoreLib.blk_mem_gen_v4_3(behavioral)
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                generic map(
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                        c_has_regceb => 0,
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                        c_has_regcea => 0,
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                        c_mem_type => 2,
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                        c_rstram_b => 0,
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                        c_rstram_a => 0,
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                        c_has_injecterr => 0,
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                        c_rst_type => "SYNC",
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                        c_prim_type => 1,
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                        c_read_width_b => 8,
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                        c_initb_val => "0",
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                        c_family => "spartan3",
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                        c_read_width_a => 8,
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                        c_disable_warn_bhv_coll => 0,
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                        c_use_softecc => 0,
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                        c_write_mode_b => "WRITE_FIRST",
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                        c_init_file_name => "no_coe_file_loaded",
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                        c_write_mode_a => "WRITE_FIRST",
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                        c_mux_pipeline_stages => 0,
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                        c_has_softecc_output_regs_b => 0,
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                        c_has_mem_output_regs_b => 0,
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                        c_has_mem_output_regs_a => 0,
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                        c_load_init_file => 0,
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                        c_xdevicefamily => "spartan3e",
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                        c_write_depth_b => 6143,
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                        c_write_depth_a => 6143,
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                        c_has_rstb => 0,
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                        c_has_rsta => 0,
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                        c_has_mux_output_regs_b => 0,
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                        c_inita_val => "0",
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                        c_has_mux_output_regs_a => 0,
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                        c_addra_width => 13,
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                        c_has_softecc_input_regs_a => 0,
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                        c_addrb_width => 13,
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                        c_default_data => "0",
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                        c_use_ecc => 0,
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                        c_algorithm => 1,
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                        c_disable_warn_bhv_range => 0,
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                        c_write_width_b => 8,
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                        c_write_width_a => 8,
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                        c_read_depth_b => 6143,
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                        c_read_depth_a => 6143,
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                        c_byte_size => 9,
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                        c_sim_collision_check => "ALL",
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                        c_common_clk => 0,
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                        c_wea_width => 1,
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                        c_has_enb => 0,
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                        c_web_width => 1,
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                        c_has_ena => 0,
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                        c_use_byte_web => 0,
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                        c_use_byte_wea => 0,
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                        c_rst_priority_b => "CE",
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                        c_rst_priority_a => "CE",
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                        c_use_default_data => 0);
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-- synthesis translate_on
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BEGIN
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-- synthesis translate_off
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U0 : wrapped_vram
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                port map (
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                        clka => clka,
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                        wea => wea,
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                        addra => addra,
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                        dina => dina,
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                        douta => douta,
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                        clkb => clkb,
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                        web => web,
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                        addrb => addrb,
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                        dinb => dinb,
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                        doutb => doutb);
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-- synthesis translate_on
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END vram_a;
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