URL https://opencores.org/ocsvn/z80soc/z80soc/trunk

Subversion Repositories z80soc

[/] [z80soc/] [trunk/] [V0.7.1a/] [S3E/] [memoryCores/] [z80socv0.7.cgc] - Blame information for rev 42

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   xilinx.com
   project
   z80socv0.7
   1.0
   
      
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               coregen
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               coregen
               ./
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            E:\FPGA Projetos\Z80SoC\V0.7.1\rom\rom.coe
            Single_Bit_Error_Injection
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               coregen
               ./
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               xc3s500e
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               BusFormatAngleBracketNotRipped
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            Single_Bit_Error_Injection
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               coregen
               ./
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               coregen
               ./
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               xc3s500e
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               fg320
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               BusFormatAngleBracketNotRipped
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            100
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            no_coe_file_loaded
            Single_Bit_Error_Injection
            ALL
            CE
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               coregen
               ./
               ./tmp/
               ./tmp/_cg
             
             
               xc3s500e
               spartan3e
               fg320
               -4
             
             
               BusFormatAngleBracketNotRipped
               VHDL
               true
               Other
               false
               false
               false
               Ngc
               false
             
             
               Behavioral
               VHDL
               false
             
           
         
      
   
   
   
      
       
         z80socv0.7
         ./
         ./tmp/
         ./tmp/_cg
       
       
         xc3s500e
         spartan3e
         fg320
         -4
       
       
         BusFormatAngleBracketNotRipped
         VHDL
         true
         Other
         false
         false
         false
         Ngc
         false
       
       
         Behavioral
         VHDL
         false
       
     
   


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Subversion Repositories z80soc

[/] [z80soc/] [trunk/] [V0.7.1a/] [S3E/] [memoryCores/] [z80socv0.7.cgc] - Blame information for rev 42

Line No.	Rev	Author	Line
1	41	rrred
2
3			`xilinx.com`
4			`project`
5			`z80socv0.7`
6			`1.0`
7
8
9			`charram2k`
10
11
12
13
14			`false`
15			`2048`
16			`WRITE_FIRST`
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18			`8`
19			`8`
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23			`True_Dual_Port_RAM`
24			`false`
25			`9`
26			`false`
27			`false`
28			`0`
29			`false`
30			`0`
31			`false`
32			`false`
33			`false`
34			`Always_Enabled`
35			`Always_Enabled`
36			`false`
37			`false`
38			`false`
39			`false`
40			`Minimum_Area`
41			`false`
42			`false`
43			`8`
44			`8`
45			`SYNC`
46			`false`
47			`0`
48			`0`
49			`true`
50			`false`
51			`F:\FPGA\Z80SoC\V0.7\rom\char.coe`
52			`Single_Bit_Error_Injection`
53			`ALL`
54			`CE`
55			`CE`
56
57
58
59
60			`coregen`
61			`./`
62			`./tmp/`
63			`./tmp/_cg`
64
65
66			`xc3s500e`
67			`spartan3e`
68			`fg320`
69			`-4`
70
71
72			`BusFormatAngleBracketNotRipped`
73			`VHDL`
74			`true`
75			`Other`
76			`false`
77			`false`
78			`false`
79			`Ngc`
80			`false`
81
82
83			`Behavioral`
84			`VHDL`
85			`false`
86
87
88
89
90
91			`lcdvram`
92
93
94
95
96			`false`
97			`32`
98			`READ_FIRST`
99			`READ_FIRST`
100			`8`
101			`8`
102			`false`
103			`false`
104			`8kx2`
105			`Simple_Dual_Port_RAM`
106			`false`
107			`9`
108			`false`
109			`false`
110			`0`
111			`false`
112			`0`
113			`false`
114			`false`
115			`false`
116			`Always_Enabled`
117			`Always_Enabled`
118			`false`
119			`false`
120			`false`
121			`false`
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124			`false`
125			`8`
126			`8`
127			`SYNC`
128			`false`
129			`0`
130			`0`
131			`false`
132			`false`
133			`no_coe_file_loaded`
134			`Single_Bit_Error_Injection`
135			`ALL`
136			`CE`
137			`CE`
138
139
140
141
142			`coregen`
143			`./`
144			`./tmp/`
145			`./tmp/_cg`
146
147
148			`xc3s500e`
149			`spartan3e`
150			`fg320`
151			`-4`
152
153
154			`BusFormatAngleBracketNotRipped`
155			`VHDL`
156			`true`
157			`Other`
158			`false`
159			`false`
160			`false`
161			`Ngc`
162			`false`
163
164
165			`Behavioral`
166			`VHDL`
167			`false`
168
169
170
171
172
173			`ram`
174
175
176
177
178			`50`
179			`false`
180			`12288`
181			`false`
182			`WRITE_FIRST`
183			`WRITE_FIRST`
184			`false`
185			`false`
186			`8`
187			`8`
188			`false`
189			`false`
190			`8kx2`
191			`Single_Port_RAM`
192			`false`
193			`9`
194			`false`
195			`0`
196			`false`
197			`0`
198			`false`
199			`false`
200			`false`
201			`Always_Enabled`
202			`Always_Enabled`
203			`100`
204			`false`
205			`false`
206			`false`
207			`false`
208			`50`
209			`Minimum_Area`
210			`false`
211			`No_ECC`
212			`100`
213			`false`
214			`100`
215			`8`
216			`8`
217			`SYNC`
218			`false`
219			`false`
220			`100`
221			`0`
222			`0`
223			`false`
224			`false`
225			`no_coe_file_loaded`
226			`Single_Bit_Error_Injection`
227			`ALL`
228			`CE`
229			`CE`
230
231
232
233
234			`coregen`
235			`./`
236			`./tmp/`
237			`./tmp/_cg`
238
239
240			`xc3s500e`
241			`spartan3e`
242			`fg320`
243			`-4`
244
245
246			`BusFormatAngleBracketNotRipped`
247			`VHDL`
248			`false`
249			`Other`
250			`false`
251			`false`
252			`false`
253			`Ngc`
254			`false`
255
256
257			`Behavioral`
258			`VHDL`
259			`false`
260
261
262
263
264
265			`ram24k`
266
267
268
269
270			`50`
271			`false`
272			`24576`
273			`false`
274			`WRITE_FIRST`
275			`WRITE_FIRST`
276			`false`
277			`false`
278			`8`
279			`8`
280			`false`
281			`false`
282			`8kx2`
283			`Single_Port_RAM`
284			`false`
285			`9`
286			`false`
287			`0`
288			`false`
289			`0`
290			`false`
291			`false`
292			`false`
293			`Always_Enabled`
294			`Always_Enabled`
295			`100`
296			`false`
297			`false`
298			`false`
299			`false`
300			`50`
301			`Minimum_Area`
302			`false`
303			`No_ECC`
304			`100`
305			`false`
306			`100`
307			`8`
308			`8`
309			`SYNC`
310			`false`
311			`false`
312			`100`
313			`0`
314			`0`
315			`false`
316			`false`
317			`no_coe_file_loaded`
318			`Single_Bit_Error_Injection`
319			`ALL`
320			`CE`
321			`CE`
322
323
324
325
326			`coregen`
327			`./`
328			`./tmp/`
329			`./tmp/_cg`
330
331
332			`xc3s500e`
333			`spartan3e`
334			`fg320`
335			`-4`
336
337
338			`BusFormatAngleBracketNotRipped`
339			`VHDL`
340			`false`
341			`Other`
342			`false`
343			`false`
344			`false`
345			`Ngc`
346			`false`
347
348
349			`Behavioral`
350			`VHDL`
351			`false`
352
353
354
355
356
357			`ram32k`
358
359
360
361
362			`false`
363			`32768`
364			`WRITE_FIRST`
365			`WRITE_FIRST`
366			`8`
367			`8`
368			`false`
369			`false`
370			`8kx2`
371			`Single_Port_RAM`
372			`false`
373			`9`
374			`false`
375			`false`
376			`0`
377			`false`
378			`0`
379			`false`
380			`false`
381			`false`
382			`Always_Enabled`
383			`Always_Enabled`
384			`false`
385			`false`
386			`false`
387			`false`
388			`Minimum_Area`
389			`false`
390			`false`
391			`8`
392			`8`
393			`SYNC`
394			`false`
395			`0`
396			`0`
397			`false`
398			`false`
399			`no_coe_file_loaded`
400			`Single_Bit_Error_Injection`
401			`ALL`
402			`CE`
403			`CE`
404
405
406
407
408			`coregen`
409			`./`
410			`./tmp/`
411			`./tmp/_cg`
412
413
414			`xc3s500e`
415			`spartan3e`
416			`fg320`
417			`-4`
418
419
420			`BusFormatAngleBracketNotRipped`
421			`VHDL`
422			`true`
423			`Other`
424			`false`
425			`false`
426			`false`
427			`Ngc`
428			`false`
429
430
431			`Behavioral`
432			`VHDL`
433			`false`
434
435
436
437
438
439			`ram8k`
440
441
442
443
444			`50`
445			`false`
446			`8192`
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449			`WRITE_FIRST`
450			`false`
451			`false`
452			`8`
453			`8`
454			`false`
455			`false`
456			`8kx2`
457			`Single_Port_RAM`
458			`false`
459			`9`
460			`false`
461			`0`
462			`false`
463			`0`
464			`false`
465			`false`
466			`false`
467			`Always_Enabled`
468			`Always_Enabled`
469			`100`
470			`false`
471			`false`
472			`false`
473			`false`
474			`50`
475			`Minimum_Area`
476			`false`
477			`No_ECC`
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479			`false`
480			`100`
481			`8`
482			`8`
483			`SYNC`
484			`false`
485			`false`
486			`100`
487			`0`
488			`0`
489			`false`
490			`false`
491			`no_coe_file_loaded`
492			`Single_Bit_Error_Injection`
493			`ALL`
494			`CE`
495			`CE`
496
497
498
499
500			`coregen`
501			`./`
502			`./tmp/`
503			`./tmp/_cg`
504
505
506			`xc3s500e`
507			`spartan3e`
508			`fg320`
509			`-4`
510
511
512			`BusFormatAngleBracketNotRipped`
513			`VHDL`
514			`false`
515			`Other`
516			`false`
517			`false`
518			`false`
519			`Ngc`
520			`false`
521
522
523			`Behavioral`
524			`VHDL`
525			`false`
526
527
528
529
530
531			`rom`
532
533
534
535
536			`0`
537			`false`
538			`16384`
539			`false`
540			`WRITE_FIRST`
541			`WRITE_FIRST`
542			`false`
543			`false`
544			`8`
545			`8`
546			`false`
547			`false`
548			`8kx2`
549			`Single_Port_ROM`
550			`false`
551			`9`
552			`false`
553			`0`
554			`false`
555			`0`
556			`false`
557			`false`
558			`false`
559			`Always_Enabled`
560			`Always_Enabled`
561			`100`
562			`false`
563			`false`
564			`false`
565			`false`
566			`0`
567			`Minimum_Area`
568			`false`
569			`No_ECC`
570			`0`
571			`false`
572			`100`
573			`8`
574			`8`
575			`SYNC`
576			`false`
577			`false`
578			`0`
579			`0`
580			`0`
581			`true`
582			`false`
583			`E:\FPGA Projetos\Z80SoC\V0.7.1\rom\rom.coe`
584			`Single_Bit_Error_Injection`
585			`ALL`
586			`CE`
587			`CE`
588
589
590
591
592			`coregen`
593			`./`
594			`./tmp/`
595			`./tmp/_cg`
596
597
598			`xc3s500e`
599			`spartan3e`
600			`fg320`
601			`-4`
602
603
604			`BusFormatAngleBracketNotRipped`
605			`VHDL`
606			`true`
607			`Other`
608			`false`
609			`false`
610			`false`
611			`Ngc`
612			`false`
613
614
615			`Behavioral`
616			`VHDL`
617			`false`
618
619
620
621
622
623			`rom8k`
624
625
626
627
628			`0`
629			`false`
630			`8192`
631			`false`
632			`WRITE_FIRST`
633			`WRITE_FIRST`
634			`false`
635			`false`
636			`8`
637			`8`
638			`false`
639			`false`
640			`8kx2`
641			`Single_Port_ROM`
642			`false`
643			`9`
644			`false`
645			`0`
646			`false`
647			`0`
648			`false`
649			`false`
650			`false`
651			`Always_Enabled`
652			`Always_Enabled`
653			`100`
654			`false`
655			`false`
656			`false`
657			`false`
658			`0`
659			`Minimum_Area`
660			`false`
661			`No_ECC`
662			`0`
663			`false`
664			`100`
665			`8`
666			`8`
667			`SYNC`
668			`false`
669			`false`
670			`0`
671			`0`
672			`0`
673			`true`
674			`false`
675			`E:\FPGA Projetos\Z80SoC\V0.7.1\rom\rom8k.coe`
676			`Single_Bit_Error_Injection`
677			`ALL`
678			`CE`
679			`CE`
680
681
682
683
684			`coregen`
685			`./`
686			`./tmp/`
687			`./tmp/_cg`
688
689
690			`xc3s500e`
691			`spartan3e`
692			`fg320`
693			`-4`
694
695
696			`BusFormatAngleBracketNotRipped`
697			`VHDL`
698			`true`
699			`Other`
700			`false`
701			`false`
702			`false`
703			`Ngc`
704			`false`
705
706
707			`Behavioral`
708			`VHDL`
709			`false`
710
711
712
713
714
715			`vram`
716
717
718
719
720			`50`
721			`false`
722			`6143`
723			`false`
724			`WRITE_FIRST`
725			`WRITE_FIRST`
726			`false`
727			`false`
728			`8`
729			`8`
730			`false`
731			`false`
732			`8kx2`
733			`True_Dual_Port_RAM`
734			`false`
735			`9`
736			`false`
737			`0`
738			`false`
739			`0`
740			`false`
741			`false`
742			`false`
743			`Always_Enabled`
744			`Always_Enabled`
745			`100`
746			`false`
747			`false`
748			`false`
749			`false`
750			`50`
751			`Minimum_Area`
752			`false`
753			`No_ECC`
754			`100`
755			`false`
756			`100`
757			`8`
758			`8`
759			`SYNC`
760			`false`
761			`false`
762			`100`
763			`0`
764			`0`
765			`false`
766			`false`
767			`no_coe_file_loaded`
768			`Single_Bit_Error_Injection`
769			`ALL`
770			`CE`
771			`CE`
772
773
774
775
776			`coregen`
777			`./`
778			`./tmp/`
779			`./tmp/_cg`
780
781
782			`xc3s500e`
783			`spartan3e`
784			`fg320`
785			`-4`
786
787
788			`BusFormatAngleBracketNotRipped`
789			`VHDL`
790			`true`
791			`Other`
792			`false`
793			`false`
794			`false`
795			`Ngc`
796			`false`
797
798
799			`Behavioral`
800			`VHDL`
801			`false`
802
803
804
805
806
807			`vram3200x8`
808
809
810
811
812			`50`
813			`false`
814			`3200`
815			`false`
816			`WRITE_FIRST`
817			`WRITE_FIRST`
818			`false`
819			`false`
820			`8`
821			`8`
822			`false`
823			`false`
824			`8kx2`
825			`True_Dual_Port_RAM`
826			`false`
827			`9`
828			`false`
829			`0`
830			`false`
831			`0`
832			`false`
833			`false`
834			`false`
835			`Always_Enabled`
836			`Always_Enabled`
837			`100`
838			`false`
839			`false`
840			`false`
841			`false`
842			`50`
843			`Minimum_Area`
844			`false`
845			`No_ECC`
846			`100`
847			`false`
848			`100`
849			`8`
850			`8`
851			`SYNC`
852			`false`
853			`false`
854			`100`
855			`0`
856			`0`
857			`false`
858			`false`
859			`no_coe_file_loaded`
860			`Single_Bit_Error_Injection`
861			`ALL`
862			`CE`
863			`CE`
864
865
866
867
868			`coregen`
869			`./`
870			`./tmp/`
871			`./tmp/_cg`
872
873
874			`xc3s500e`
875			`spartan3e`
876			`fg320`
877			`-4`
878
879
880			`BusFormatAngleBracketNotRipped`
881			`VHDL`
882			`true`
883			`Other`
884			`false`
885			`false`
886			`false`
887			`Ngc`
888			`false`
889
890
891			`Behavioral`
892			`VHDL`
893			`false`
894
895
896
897
898
899
900
901
902
903			`z80socv0.7`
904			`./`
905			`./tmp/`
906			`./tmp/_cg`
907
908
909			`xc3s500e`
910			`spartan3e`
911			`fg320`
912			`-4`
913
914
915			`BusFormatAngleBracketNotRipped`
916			`VHDL`
917			`true`
918			`Other`
919			`false`
920			`false`
921			`false`
922			`Ngc`
923			`false`
924
925
926			`Behavioral`
927			`VHDL`
928			`false`
929
930
931
932