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[/] [z80soc/] [trunk/] [V0.7.1a/] [S3E/] [vhdl/] [top_s3e.vhd] - Blame information for rev 45

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-------------------------------------------------------------------------------------------------
-- Z80SoC (Z80 System on Chip)
-- Ronivon Candido Costa
-- ronivon.costa@gmail.com
--
-- Version history:
-------------------
-- version 0.7.1
-- 2010 / 11 / 22
-- Change memory layout and increased Rom, using Megawizard plug in manager
-- Memory cores redefined
-- Fixed bug in the video.vhd
-- New rom demo in C (SDCC)
--
-- version 0.7 for Spartan 3E
-- Release Date: 2010 / 02 / 17
--
-- version 0.6 for Spartan 3E
-- Release Date: 2008 / 05 / 21
--
-- Version 0.5 Beta for Spartan 3E
-- Developer: Ronivon Candido Costa
-- Release Date: 2008 / 05 / 01
--
-- Based on the T80 core: http://www.opencores.org/projects.cgi/web/t80
-- This version developed and tested on: Diligent Spartan 3E
--
-- Architecture of z80soc:
-- Processor: Z80 Processor (T80 core) Runnig at 3.58 Mhz (can be changed)
--
-- External devices/resources:
-- 
--      16 KB   ROM                     Read                    (0x0000h - 0x3FFFh)
--      08 KB           Video RAM               Read/Write              (0x4000h - 0x4C7Fh)
--      02 KB           Char RAM                Read/Write              (0x4C80h - 0x547FH)
--                      Not used                                        (0x5480h - 0x5FFFh)     
--      24 KB           RAM                     Read/Write              (0x6000h - 0xBFFFh)
--                      Not Used                                        (0xC000h - 0xFFDFh)
--      01              LCD display             Write                   (0xFFE0h - 0xFFFFh)
--      08              Green Leds              Out                     (Port 0x01h)
--      04              Switches                In                      (Port 0x20h)
--      04              Push buttons    In                      (Port 0x30h)
--      01              Rotary Knob             In                      (Port 0x70h)
--      01              PS/2 keyboard   In                      (Port 0x80h)
--      01              Video write             Out                     (Port 0x90h)
--
--  Revision history:
--
-- 2008/05/20 - Modified RAM layout to support new and future improvements
--            - Added port 0x90 to write a character to video.
--            - Cursor x,y automatically updated after writing to port 0x90
--            - Added port 0x91 for video cursor X
--            - Added port 0x92 for video cursor Y
--                 - Updated ROM to demonstrate how to use these new resources
--            - Changed ROM to support 14 bit addresses (16 Kb)
--
-- 2008/05/12 - Added support for the Rotary Knob
--            - ROT_CENTER push button (Knob) reserved for RESET
--            - The four push buttons are now available for the user (Port 0x30)
--
-- 2008/05/11 - Fixed access to RAM and VRAM,
--              Released same ROM version for DE1 and S3E
--
-- 2008/05/01 - Added LCD support for Spartan 3E
--
-- 2008/04(21 - Release of Version 0.5-S3E-Beta for Diligent Spartan 3E
--
--      2008/04/17 - Added Video support for 40x30 mode
--
-- 2008/04/16 - Release of Version 0.5-DE1-Beta for Altera DE1
--
-- TO-DO:
-- - Implement hardware control for the A/D and IO pins
-- - Monitor program to introduce Z80 Assmebly codes and run
--      - Serial communication, to download assembly code from PC
--      - Add hardware support for 80x40 Video out
--      - SD/MMC card interface to read/store data and programs
-------------------------------------------------------------------------------------------------
 
-- use IEEE.numeric_std.all;
 
library IEEE;
use  IEEE.STD_LOGIC_1164.all;
use  IEEE.STD_LOGIC_ARITH.all;
use  IEEE.STD_LOGIC_UNSIGNED.all;
 
entity Z80SOC_TOP is
port(
        CLOCK_50        : in std_logic;
        KEY             : in std_logic_vector(3 downto 0);               -- Push buttons
        SW              : in std_logic_vector(3 downto 0);               -- Switches
        LEDG            : out std_logic_vector(7 downto 0);              -- Green LEDs
        PS2_DAT,                                                                -- Data
        PS2_CLK : inout std_logic;                              -- Clock
        VGA_HS,                                                         -- H_SYNC
        VGA_VS  : out std_logic;                                        -- SYNC
        VGA_R,                                                          -- Red[3:0]
        VGA_G,                                                          -- Green[3:0]
        VGA_B   : out std_logic;                                        -- Blue[3:0]
        SF_D            : out std_logic_vector(3 downto 0);
        LCD_E,
        LCD_RS,
        LCD_RW,
        SF_CE0  : out std_logic;
        ROT_A,
        ROT_B,
        ROT_CENTER      : in std_logic
);
end Z80SOC_TOP;
 
architecture rtl of Z80SOC_TOP is
 
        use work.z80soc_pack.all;
 
        component T80se
        generic(
                Mode                    : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
                T2Write                 : integer := 1; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
                IOWait          : integer := 1  -- 0 => Single cycle I/O, 1 => Std I/O cycle
        );
        port(
                RESET_n         : in std_logic;
                CLK_n                   : in std_logic;
                CLKEN                   : in std_logic;
                WAIT_n          : in std_logic;
                INT_n                   : in std_logic;
                NMI_n                   : in std_logic;
                BUSRQ_n         : in std_logic;
                M1_n                    : out std_logic;
                MREQ_n          : out std_logic;
                IORQ_n          : out std_logic;
                RD_n                    : out std_logic;
                WR_n                    : out std_logic;
                RFSH_n          : out std_logic;
                HALT_n          : out std_logic;
                BUSAK_n         : out std_logic;
                A                       : out std_logic_vector(15 downto 0);
                DI                      : in std_logic_vector(7 downto 0);
                DO                      : out std_logic_vector(7 downto 0)
        );
        end component;
 
        component ram
        port (
                clka: IN std_logic;
                wea: IN std_logic_VECTOR(0 downto 0);
                addra: IN std_logic_VECTOR(13 downto 0);
                dina: IN std_logic_VECTOR(7 downto 0);
                douta: OUT std_logic_VECTOR(7 downto 0));
        end component;
 
        component rom
        port (
                clka: IN std_logic;
                addra: IN std_logic_VECTOR(13 downto 0);
                douta: OUT std_logic_VECTOR(7 downto 0));
        end component;
 
        component Clock_357Mhz
        PORT (
                clock_50Mhz             : IN    STD_LOGIC;
                clock_357Mhz    : OUT   STD_LOGIC);
        end component;
 
        component clk_div
        PORT
        (
                clock_25Mhz             : IN    STD_LOGIC;
                clock_1MHz              : OUT   STD_LOGIC;
                clock_100KHz    : OUT   STD_LOGIC;
                clock_10KHz             : OUT   STD_LOGIC;
                clock_1KHz              : OUT   STD_LOGIC;
                clock_100Hz             : OUT   STD_LOGIC;
                clock_10Hz              : OUT   STD_LOGIC;
                clock_1Hz               : OUT   STD_LOGIC);
        end component;
 
        component lcd
        port(
                clk,
                reset                   : in std_logic;
                SF_D                    : out std_logic_vector(3 downto 0);
                LCD_E,
                LCD_RS,
                LCD_RW,
                SF_CE0          : out std_logic;
                lcd_addr                : out std_logic_vector(4 downto 0);
                lcd_char                : in std_logic_vector(7 downto 0));
        end component;
 
        component lcdvram
        port (
                addra                   : IN std_logic_VECTOR(4 downto 0);
                addrb                   : IN std_logic_VECTOR(4 downto 0);
                clka                    : IN std_logic;
                clkb                    : IN std_logic;
                dina                    : IN std_logic_VECTOR(7 downto 0);
                doutb                   : OUT std_logic_VECTOR(7 downto 0);
                wea                     : IN std_logic_VECTOR(0 downto 0));
        end component;
 
        component ps2kbd
        PORT (
                keyboard_clk    : inout std_logic;
                keyboard_data   : inout std_logic;
                clock                   : in std_logic;
                clkdelay                : in std_logic;
                reset                   : in std_logic;
                read                    : in std_logic;
                scan_ready              : out std_logic;
                ps2_ascii_code  : out std_logic_vector(7 downto 0));
        end component;
 
        component vram
        port (
                addra                   : IN std_logic_VECTOR(12 downto 0);
                addrb                   : IN std_logic_VECTOR(12 downto 0);
                clka                    : IN std_logic;
                clkb                    : IN std_logic;
                dina                    : IN std_logic_VECTOR(7 downto 0);
                dinb                    : IN std_logic_VECTOR(7 downto 0);
                douta                   : OUT std_logic_VECTOR(7 downto 0);
                doutb                   : OUT std_logic_VECTOR(7 downto 0);
                wea                     : IN std_logic_VECTOR(0 downto 0);
                web                     : IN std_logic_VECTOR(0 downto 0));
        end component;
 
        component charram2k
        port (
                addra                   : IN std_logic_VECTOR(10 downto 0);
                addrb                   : IN std_logic_VECTOR(10 downto 0);
                clka                    : IN std_logic;
                clkb                    : IN std_logic;
                dina                    : IN std_logic_VECTOR(7 downto 0);
                dinb                    : IN std_logic_VECTOR(7 downto 0);
                douta                   : OUT std_logic_VECTOR(7 downto 0);
                doutb                   : OUT std_logic_VECTOR(7 downto 0);
                wea                     : IN std_logic_VECTOR(0 downto 0);
                web                     : IN std_logic_VECTOR(0 downto 0));
        end component;
 
        COMPONENT video
        PORT (
                CLOCK_25                : IN STD_LOGIC;
                VRAM_DATA               : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
                VRAM_ADDR               : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
                VRAM_CLOCK              : OUT STD_LOGIC;
                VRAM_WREN               : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
                CRAM_DATA               : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
                CRAM_ADDR               : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
                CRAM_WEB                        : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
                VGA_R,
                VGA_G,
                VGA_B                           : OUT STD_LOGIC;
                VGA_HS,
                VGA_VS                  : OUT STD_LOGIC);
        END COMPONENT;
 
        COMPONENT ROT_CTRL
        PORT (
                CLOCK                   : IN STD_LOGIC;
                ROT_A                   : IN    STD_LOGIC;
                ROT_B                   : IN    STD_LOGIC;
                DIRECTION               : OUT   STD_LOGIC_VECTOR(1 DOWNTO 0));
        END COMPONENT;
 
        signal MREQ_n           : std_logic := '0';
        signal IORQ_n           : std_logic := '1';
        signal RD_n                     : std_logic := '0';
        signal WR_n                     : std_logic := '1';
        signal Rst_n_s          : std_logic;
        signal Clk_Z80          : std_logic;
        signal DI_CPU           : std_logic_vector(7 downto 0);
        signal DO_CPU           : std_logic_vector(7 downto 0);
        signal A                                : std_logic_vector(15 downto 0);
        signal One                      : std_logic := '1';
 
        signal D_ROM            : std_logic_vector(7 downto 0);
 
        signal clk25mhz         : std_logic;
        signal clk100hz         : std_logic;
        signal clk10hz          : std_logic;
        signal clk1hz           : std_logic;
 
        signal vram_addra               : std_logic_vector(15 downto 0);
        signal vram_addrb               : std_logic_vector(15 downto 0);
        signal vram_dina                : std_logic_vector(7 downto 0);
        signal vram_dinb                : std_logic_vector(7 downto 0);
        signal vram_douta               : std_logic_vector(7 downto 0);
        signal vram_doutb               : std_logic_vector(7 downto 0);
        signal vram_wea         : std_logic_VECTOR(0 downto 0) := "1";
        signal vram_web         : std_logic_VECTOR(0 downto 0) := "1";
        signal vram_clka                : std_logic;
        signal vram_clkb                : std_logic;
 
        signal cram_addra               : std_logic_vector(15 downto 0);
        signal cram_addrb               : std_logic_vector(15 downto 0);
        signal cram_dina                : std_logic_vector(7 downto 0);
        signal cram_dinb                : std_logic_vector(7 downto 0);
        signal cram_douta               : std_logic_vector(7 downto 0);
        signal cram_doutb               : std_logic_vector(7 downto 0);
        signal cram_wea         : std_logic_VECTOR(0 downto 0) := "1";
        signal cram_web         : std_logic_VECTOR(0 downto 0) := "1";
        signal cram_clka                : std_logic;
        signal cram_clkb                : std_logic;
 
        signal vram_douta_reg: std_logic_vector(7 downto 0);
        signal VID_CURSOR               : std_logic_vector(15 downto 0);
        signal CURSOR_X         : std_logic_vector(6 downto 0);
        signal CURSOR_Y         : std_logic_vector(5 downto 0);
 
        -- sram signals
        signal sram_addr                : std_logic_vector(15 downto 0);
        signal sram_din         : std_logic_vector(7 downto 0);
        signal sram_dout                : std_logic_vector(7 downto 0);
        signal sram_we                  : std_logic_vector(0 downto 0) := "1";
 
        -- LCD signals
        signal lcd_wea                  : std_logic_VECTOR(0 downto 0) := "1";
        signal lcd_addra                : std_logic_vector(4 downto 0);
        signal lcd_addrb                : std_logic_vector(4 downto 0);
        signal lcd_dina         : std_logic_vector(7 downto 0);
        signal lcd_doutb                : std_logic_vector(7 downto 0);
 
        -- VGA conversion from 4 bits to 8 bit
        signal VGA_Rs,
               VGA_Gs,
               VGA_Bs           : std_logic_vector(3 downto 0);
        signal VGA_HSs,
               VGA_VSs          : std_logic;
 
        -- PS/2 Keyboard
        signal ps2_read         : std_logic;
        signal ps2_scan_ready   : std_logic;
        signal ps2_ascii_sig    : std_logic_vector(7 downto 0);
        signal ps2_ascii_reg1   : std_logic_vector(7 downto 0);
        signal ps2_ascii_reg    : std_logic_vector(7 downto 0);
 
        -- Rotary Control
        signal rot_dir          : std_logic_vector(1 downto 0);
        signal rot_dir_sig      : std_logic_vector(1 downto 0);
 
        signal Z80SOC_VERSION           : std_logic_vector(2 downto 0);   -- "000" = DE1, "001" = S3E
 
begin
 
        Z80SOC_VERSION <= "001";                -- "000" = DE1, "001" = S3E
        Rst_n_s <= not ROT_CENTER;
 
--      Write into VRAM
        vram_addra <= VID_CURSOR when (IORQ_n = '0' and MREQ_n = '1' and A(7 downto 0) = x"90")  else
                      A - x"4000" when (A >= x"4000" and A < x"5800");
        vram_wea(0) <= '0' when ((A >= x"4000" and A < x"5800" and Wr_n = '0' and MReq_n = '0') or (Wr_n = '0' and IORQ_n = '0' and A(7 downto 0) = x"90")) else
                '1';
        vram_dina <= DO_CPU;
 
-- Write into char ram
        cram_addra      <= A - x"5800";
        cram_dina       <= DO_CPU;
        cram_wea(0)      <= '0' when (A >= x"5800" and A < x"6000" and Wr_n = '0' and MReq_n = '0') else '1';
 
-- Write into LCD video ram
        lcd_addra <= A - x"FFE0";
        lcd_dina <= DO_CPU;
        lcd_wea(0) <= '0' when (A >= x"FFE0" and A <= x"FFFF" and Wr_n = '0' and MReq_n = '0') else '1';
 
-- Write into SRAM
        sram_addr <= A - x"6000";
        sram_din <= DO_CPU;
        sram_we(0) <= '0' when (A >= x"6000" and A < x"FFE0" and Wr_n = '0' and MReq_n = '0') else '1';
 
        DI_CPU <=       ("00000" & Z80SOC_VERSION) when (Rd_n = '0' and MREQ_n = '0' and A = x"52C0") else
                        D_ROM when (Rd_n = '0' and MREQ_n = '0' and IORQ_n = '1' and A < x"4000") else
                        vram_douta when (MREQ_n = '0' and IORQ_n = '1' and Rd_n = '0' and A < x"5800") else
                        cram_douta when (MREQ_n = '0' and IORQ_n = '1' and Rd_n = '0' and A < x"6000") else
                        sram_dout when (Rd_n = '0' and MREQ_n = '0' and IORQ_n = '1' and A < x"FFE0") else
                        ("0000" & SW) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"20") else
                        ("0000" & KEY) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"30") else
                        ("000000" & rot_dir) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"70") else
                        ps2_ascii_reg when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"80") else
                        ("0" & CURSOR_X) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"91") else
                        ("00" & CURSOR_Y) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"92") else
                        "ZZZZZZZZ";
 
        -- Process to latch leds and hex displays
        pinout_process: process(Clk_Z80)
        variable LEDG_sig               : std_logic_vector(7 downto 0);
        begin
                if Clk_Z80'event and Clk_Z80 = '1' then
                  if IORQ_n = '0' and Wr_n = '0' then
                        -- LEDG
                        if A(7 downto 0) = x"01" then
                                LEDG_sig := DO_CPU;
                        end if;
                  end if;
                end if;
                -- Latches the signals
                LEDG <= LEDG_sig;
        end process;
 
        cursorxy: process (Clk_Z80)
        variable VID_X  : std_logic_vector(6 downto 0);
        variable VID_Y  : std_logic_vector(5 downto 0);
        begin
                if Clk_Z80'event and Clk_Z80 = '1' then
                        if (IORQ_n = '0' and MREQ_n = '1' and Wr_n = '0' and A(7 downto 0) = x"91") then
                                VID_X := DO_CPU(6 downto 0);
                        elsif (IORQ_n = '0' and MREQ_n = '1' and Wr_n = '0' and A(7 downto 0) = x"92") then
                                VID_Y := DO_CPU(5 downto 0);
                        elsif (IORQ_n = '0' and MREQ_n = '1' and Wr_n = '0' and A(7 downto 0) = x"90") then
                                if VID_X = vid_cols - 1 then
                                        VID_X := "0000000";
                                        if VID_Y = vid_lines - 1 then
                                                VID_Y := "000000";
                                        else
                                                VID_Y := VID_Y + 1;
                                        end if;
                                else
                                        VID_X := VID_X + 1;
                                end if;
                        end if;
                end if;
                VID_CURSOR <= vram_base_addr + ( VID_X + ( VID_Y * conv_std_logic_vector(vid_cols,7)));
                CURSOR_X <= VID_X;
                CURSOR_Y <= VID_Y;
        end process;
 
        -- the following three processes deals with different clock domain signals
        ps2_process1: process(CLOCK_50)
        begin
                if CLOCK_50'event and CLOCK_50 = '1' then
                        if ps2_read = '1' then
                                if ps2_ascii_sig /= x"FF" then
                                        ps2_read <= '0';
                                        ps2_ascii_reg1 <= "00000000";
                                end if;
                        elsif ps2_scan_ready = '1' then
                                if ps2_ascii_sig = x"FF" then
                                        ps2_read <= '1';
                                else
                                        ps2_ascii_reg1 <= ps2_ascii_sig;
                                end if;
                        end if;
                end if;
        end process;
 
        ps2_process2: process(Clk_Z80)
        variable stack  : std_logic_vector(15 downto 0):=x"7FDE";
        begin
                if Clk_Z80'event and Clk_Z80 = '1' then
                        ps2_ascii_reg <= ps2_ascii_reg1;
                end if;
        end process;
 
        rot_process: process(clk100hz)
        begin
                if clk100hz'event and clk100hz = '1' then
                        rot_dir <= rot_dir_sig;
                end if;
        end process;
 
        One <= '1';
        z80_inst: T80se
                port map (
                        M1_n => open,
                        MREQ_n => MReq_n,
                        IORQ_n => IORq_n,
                        RD_n => Rd_n,
                        WR_n => Wr_n,
                        RFSH_n => open,
                        HALT_n => open,
                        WAIT_n => One,
                        INT_n => One,
                        NMI_n => One,
                        RESET_n => Rst_n_s,
                        BUSRQ_n => One,
                        BUSAK_n => open,
                        CLK_n => Clk_Z80,
                        CLKEN => One,
                        A => A,
                        DI => DI_CPU,
                        DO => DO_CPU
                );
 
        ps2_kbd_inst : ps2kbd PORT MAP (
                keyboard_clk    => PS2_CLK,
                keyboard_data   => PS2_DAT,
                clock                   => CLOCK_50,
                clkdelay                => clk100hz,
                reset                   => Rst_n_s,
                read                    => ps2_read,
                scan_ready              => ps2_scan_ready,
                ps2_ascii_code  => ps2_ascii_sig
        );
 
        clk25mhz_proc: process (CLOCK_50)
   begin
                if CLOCK_50'event and CLOCK_50 = '1' then
        clk25mhz <= not clk25mhz;
                end if;
   end process;
 
   clkdiv_inst: clk_div
                port map (
                clock_25Mhz             => clk25mhz,
                clock_1MHz              => open,
                clock_100KHz    => open,
                clock_10KHz             => open,
                clock_1KHz              => open,
                clock_100Hz             => clk100hz,
                clock_10Hz              => clk10hz,
                clock_1Hz               => clk1hz
        );
 
        clock_z80_inst : Clock_357Mhz
        port map (
                clock_50Mhz             => CLOCK_50,
                clock_357Mhz    => Clk_Z80
        );
 
        lcd_inst: lcd
        port map (
                clk                     => CLOCK_50,
                reset                   => not Rst_n_s,
                SF_D                    => SF_D,
                LCD_E                   => LCD_E,
                LCD_RS          => LCD_RS,
                LCD_RW          => LCD_RW,
                SF_CE0          => SF_CE0,
                lcd_addr                => lcd_addrb,
                lcd_char                => lcd_doutb
        );
 
        video_inst: video port map (
                        CLOCK_25                        => clk25mhz,
                        VRAM_DATA               => vram_doutb,
                        VRAM_ADDR               => vram_addrb(12 downto 0),
                        VRAM_CLOCK              => vram_clkb,
                        VRAM_WREN               => vram_web,
                        CRAM_DATA               => cram_doutb,
                        CRAM_ADDR               => cram_addrb(10 downto 0),
                        CRAM_WEB                        => cram_web,
                        VGA_R                           => VGA_R,
                        VGA_G                           => VGA_G,
                        VGA_B                           => VGA_B,
                        VGA_HS                  => VGA_HS,
                        VGA_VS                  => VGA_VS
        );
 
        vram_inst : vram
                port map (
                        addra   => vram_addra(12 downto 0),
                        addrb   => vram_addrb(12 downto 0),
                        clka            => Clk_Z80,
                        clkb            => vram_clkb,
                        dina            => vram_dina,
                        dinb            => vram_dinb,
                        douta   => vram_douta,
                        doutb   => vram_doutb,
                        wea             => NOT vram_wea,
                        web             => NOT vram_web);
 
        cram: charram2k
                port map (
                        addra   => cram_addra(10 downto 0),
                        addrb   => cram_addrb(10 downto 0),
                        clka            => Clk_Z80,
                        clkb            => vram_clkb,
                        dina            => cram_dina,
                        dinb            => cram_dinb,
                        douta   => cram_douta,
                        doutb   => cram_doutb,
                        wea             => NOT cram_wea,
                        web             => NOT cram_web);
 
        lcdvram_inst : lcdvram
                port map (
                        addra => lcd_addra,
                        addrb => lcd_addrb,
                        clka => Clk_Z80,
                        clkb => CLOCK_50,
                        dina => lcd_dina,
                        doutb => lcd_doutb,
                        wea => NOT lcd_wea
                );
 
        rom_inst : rom
        port map (
                clka => Clk_Z80,
                addra => A(13 downto 0),
                douta => D_ROM
        );
 
        ram_inst : ram
                port map (
                        clka            => Clk_Z80,
                        dina            => sram_din,
                        addra   => sram_addr(13 downto 0),
                        wea             => NOT sram_we,
                        douta   => sram_dout);
 
        rotary_inst : ROT_CTRL
                port map (
                        CLOCK                   => CLOCK_50,
                        ROT_A                   => ROT_A,
                        ROT_B                   => ROT_B,
                        DIRECTION       => rot_dir_sig
        );
 
end;
 

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[/] [z80soc/] [trunk/] [V0.7.1a/] [S3E/] [vhdl/] [top_s3e.vhd] - Blame information for rev 45

Line No.	Rev	Author	Line
1	41	rrred	`-------------------------------------------------------------------------------------------------`
2			`-- Z80SoC (Z80 System on Chip)`
3			`-- Ronivon Candido Costa`
4			`-- ronivon.costa@gmail.com`
5			`--`
6			`-- Version history:`
7			`-------------------`
8			`-- version 0.7.1`
9			`-- 2010 / 11 / 22`
10			`-- Change memory layout and increased Rom, using Megawizard plug in manager`
11			`-- Memory cores redefined`
12			`-- Fixed bug in the video.vhd`
13			`-- New rom demo in C (SDCC)`
14			`--`
15			`-- version 0.7 for Spartan 3E`
16			`-- Release Date: 2010 / 02 / 17`
17			`--`
18			`-- version 0.6 for Spartan 3E`
19			`-- Release Date: 2008 / 05 / 21`
20			`--`
21			`-- Version 0.5 Beta for Spartan 3E`
22			`-- Developer: Ronivon Candido Costa`
23			`-- Release Date: 2008 / 05 / 01`
24			`--`
25			`-- Based on the T80 core: http://www.opencores.org/projects.cgi/web/t80`
26			`-- This version developed and tested on: Diligent Spartan 3E`
27			`--`
28			`-- Architecture of z80soc:`
29			`-- Processor: Z80 Processor (T80 core) Runnig at 3.58 Mhz (can be changed)`
30			`--`
31			`-- External devices/resources:`
32			`--`
33			`-- 16 KB ROM Read (0x0000h - 0x3FFFh)`
34			`-- 08 KB Video RAM Read/Write (0x4000h - 0x4C7Fh)`
35			`-- 02 KB Char RAM Read/Write (0x4C80h - 0x547FH)`
36			`-- Not used (0x5480h - 0x5FFFh)`
37			`-- 24 KB RAM Read/Write (0x6000h - 0xBFFFh)`
38			`-- Not Used (0xC000h - 0xFFDFh)`
39			`-- 01 LCD display Write (0xFFE0h - 0xFFFFh)`
40			`-- 08 Green Leds Out (Port 0x01h)`
41			`-- 04 Switches In (Port 0x20h)`
42			`-- 04 Push buttons In (Port 0x30h)`
43			`-- 01 Rotary Knob In (Port 0x70h)`
44			`-- 01 PS/2 keyboard In (Port 0x80h)`
45			`-- 01 Video write Out (Port 0x90h)`
46			`--`
47			`-- Revision history:`
48			`--`
49			`-- 2008/05/20 - Modified RAM layout to support new and future improvements`
50			`-- - Added port 0x90 to write a character to video.`
51			`-- - Cursor x,y automatically updated after writing to port 0x90`
52			`-- - Added port 0x91 for video cursor X`
53			`-- - Added port 0x92 for video cursor Y`
54			`-- - Updated ROM to demonstrate how to use these new resources`
55			`-- - Changed ROM to support 14 bit addresses (16 Kb)`
56			`--`
57			`-- 2008/05/12 - Added support for the Rotary Knob`
58			`-- - ROT_CENTER push button (Knob) reserved for RESET`
59			`-- - The four push buttons are now available for the user (Port 0x30)`
60			`--`
61			`-- 2008/05/11 - Fixed access to RAM and VRAM,`
62			`-- Released same ROM version for DE1 and S3E`
63			`--`
64			`-- 2008/05/01 - Added LCD support for Spartan 3E`
65			`--`
66			`-- 2008/04(21 - Release of Version 0.5-S3E-Beta for Diligent Spartan 3E`
67			`--`
68			`-- 2008/04/17 - Added Video support for 40x30 mode`
69			`--`
70			`-- 2008/04/16 - Release of Version 0.5-DE1-Beta for Altera DE1`
71			`--`
72			`-- TO-DO:`
73			`-- - Implement hardware control for the A/D and IO pins`
74			`-- - Monitor program to introduce Z80 Assmebly codes and run`
75			`-- - Serial communication, to download assembly code from PC`
76			`-- - Add hardware support for 80x40 Video out`
77			`-- - SD/MMC card interface to read/store data and programs`
78			`-------------------------------------------------------------------------------------------------`
79
80			`-- use IEEE.numeric_std.all;`
81
82			`library IEEE;`
83			`use IEEE.STD_LOGIC_1164.all;`
84			`use IEEE.STD_LOGIC_ARITH.all;`
85			`use IEEE.STD_LOGIC_UNSIGNED.all;`
86
87			`entity Z80SOC_TOP is`
88			`port(`
89			`CLOCK_50 : in std_logic;`
90			`KEY : in std_logic_vector(3 downto 0); -- Push buttons`
91			`SW : in std_logic_vector(3 downto 0); -- Switches`
92			`LEDG : out std_logic_vector(7 downto 0); -- Green LEDs`
93			`PS2_DAT, -- Data`
94			`PS2_CLK : inout std_logic; -- Clock`
95			`VGA_HS, -- H_SYNC`
96			`VGA_VS : out std_logic; -- SYNC`
97			`VGA_R, -- Red[3:0]`
98			`VGA_G, -- Green[3:0]`
99			`VGA_B : out std_logic; -- Blue[3:0]`
100			`SF_D : out std_logic_vector(3 downto 0);`
101			`LCD_E,`
102			`LCD_RS,`
103			`LCD_RW,`
104			`SF_CE0 : out std_logic;`
105			`ROT_A,`
106			`ROT_B,`
107			`ROT_CENTER : in std_logic`
108			`);`
109			`end Z80SOC_TOP;`
110
111			`architecture rtl of Z80SOC_TOP is`
112
113			`use work.z80soc_pack.all;`
114
115			`component T80se`
116			`generic(`
117			`Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB`
118			`T2Write : integer := 1; -- 0 => WR_n active in T3, /=0 => WR_n active in T2`
119			`IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle`
120			`);`
121			`port(`
122			`RESET_n : in std_logic;`
123			`CLK_n : in std_logic;`
124			`CLKEN : in std_logic;`
125			`WAIT_n : in std_logic;`
126			`INT_n : in std_logic;`
127			`NMI_n : in std_logic;`
128			`BUSRQ_n : in std_logic;`
129			`M1_n : out std_logic;`
130			`MREQ_n : out std_logic;`
131			`IORQ_n : out std_logic;`
132			`RD_n : out std_logic;`
133			`WR_n : out std_logic;`
134			`RFSH_n : out std_logic;`
135			`HALT_n : out std_logic;`
136			`BUSAK_n : out std_logic;`
137			`A : out std_logic_vector(15 downto 0);`
138			`DI : in std_logic_vector(7 downto 0);`
139			`DO : out std_logic_vector(7 downto 0)`
140			`);`
141			`end component;`
142
143			`component ram`
144			`port (`
145			`clka: IN std_logic;`
146			`wea: IN std_logic_VECTOR(0 downto 0);`
147			`addra: IN std_logic_VECTOR(13 downto 0);`
148			`dina: IN std_logic_VECTOR(7 downto 0);`
149			`douta: OUT std_logic_VECTOR(7 downto 0));`
150			`end component;`
151
152			`component rom`
153			`port (`
154			`clka: IN std_logic;`
155			`addra: IN std_logic_VECTOR(13 downto 0);`
156			`douta: OUT std_logic_VECTOR(7 downto 0));`
157			`end component;`
158
159			`component Clock_357Mhz`
160			`PORT (`
161			`clock_50Mhz : IN STD_LOGIC;`
162			`clock_357Mhz : OUT STD_LOGIC);`
163			`end component;`
164
165			`component clk_div`
166			`PORT`
167			`(`
168			`clock_25Mhz : IN STD_LOGIC;`
169			`clock_1MHz : OUT STD_LOGIC;`
170			`clock_100KHz : OUT STD_LOGIC;`
171			`clock_10KHz : OUT STD_LOGIC;`
172			`clock_1KHz : OUT STD_LOGIC;`
173			`clock_100Hz : OUT STD_LOGIC;`
174			`clock_10Hz : OUT STD_LOGIC;`
175			`clock_1Hz : OUT STD_LOGIC);`
176			`end component;`
177
178			`component lcd`
179			`port(`
180			`clk,`
181			`reset : in std_logic;`
182			`SF_D : out std_logic_vector(3 downto 0);`
183			`LCD_E,`
184			`LCD_RS,`
185			`LCD_RW,`
186			`SF_CE0 : out std_logic;`
187			`lcd_addr : out std_logic_vector(4 downto 0);`
188			`lcd_char : in std_logic_vector(7 downto 0));`
189			`end component;`
190
191			`component lcdvram`
192			`port (`
193			`addra : IN std_logic_VECTOR(4 downto 0);`
194			`addrb : IN std_logic_VECTOR(4 downto 0);`
195			`clka : IN std_logic;`
196			`clkb : IN std_logic;`
197			`dina : IN std_logic_VECTOR(7 downto 0);`
198			`doutb : OUT std_logic_VECTOR(7 downto 0);`
199			`wea : IN std_logic_VECTOR(0 downto 0));`
200			`end component;`
201
202			`component ps2kbd`
203			`PORT (`
204			`keyboard_clk : inout std_logic;`
205			`keyboard_data : inout std_logic;`
206			`clock : in std_logic;`
207			`clkdelay : in std_logic;`
208			`reset : in std_logic;`
209			`read : in std_logic;`
210			`scan_ready : out std_logic;`
211			`ps2_ascii_code : out std_logic_vector(7 downto 0));`
212			`end component;`
213
214			`component vram`
215			`port (`
216			`addra : IN std_logic_VECTOR(12 downto 0);`
217			`addrb : IN std_logic_VECTOR(12 downto 0);`
218			`clka : IN std_logic;`
219			`clkb : IN std_logic;`
220			`dina : IN std_logic_VECTOR(7 downto 0);`
221			`dinb : IN std_logic_VECTOR(7 downto 0);`
222			`douta : OUT std_logic_VECTOR(7 downto 0);`
223			`doutb : OUT std_logic_VECTOR(7 downto 0);`
224			`wea : IN std_logic_VECTOR(0 downto 0);`
225			`web : IN std_logic_VECTOR(0 downto 0));`
226			`end component;`
227
228			`component charram2k`
229			`port (`
230			`addra : IN std_logic_VECTOR(10 downto 0);`
231			`addrb : IN std_logic_VECTOR(10 downto 0);`
232			`clka : IN std_logic;`
233			`clkb : IN std_logic;`
234			`dina : IN std_logic_VECTOR(7 downto 0);`
235			`dinb : IN std_logic_VECTOR(7 downto 0);`
236			`douta : OUT std_logic_VECTOR(7 downto 0);`
237			`doutb : OUT std_logic_VECTOR(7 downto 0);`
238			`wea : IN std_logic_VECTOR(0 downto 0);`
239			`web : IN std_logic_VECTOR(0 downto 0));`
240			`end component;`
241
242			`COMPONENT video`
243			`PORT (`
244			`CLOCK_25 : IN STD_LOGIC;`
245			`VRAM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
246			`VRAM_ADDR : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);`
247			`VRAM_CLOCK : OUT STD_LOGIC;`
248			`VRAM_WREN : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);`
249			`CRAM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
250			`CRAM_ADDR : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);`
251			`CRAM_WEB : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);`
252			`VGA_R,`
253			`VGA_G,`
254			`VGA_B : OUT STD_LOGIC;`
255			`VGA_HS,`
256			`VGA_VS : OUT STD_LOGIC);`
257			`END COMPONENT;`
258
259			`COMPONENT ROT_CTRL`
260			`PORT (`
261			`CLOCK : IN STD_LOGIC;`
262			`ROT_A : IN STD_LOGIC;`
263			`ROT_B : IN STD_LOGIC;`
264			`DIRECTION : OUT STD_LOGIC_VECTOR(1 DOWNTO 0));`
265			`END COMPONENT;`
266
267			`signal MREQ_n : std_logic := '0';`
268			`signal IORQ_n : std_logic := '1';`
269			`signal RD_n : std_logic := '0';`
270			`signal WR_n : std_logic := '1';`
271			`signal Rst_n_s : std_logic;`
272			`signal Clk_Z80 : std_logic;`
273			`signal DI_CPU : std_logic_vector(7 downto 0);`
274			`signal DO_CPU : std_logic_vector(7 downto 0);`
275			`signal A : std_logic_vector(15 downto 0);`
276			`signal One : std_logic := '1';`
277
278			`signal D_ROM : std_logic_vector(7 downto 0);`
279
280			`signal clk25mhz : std_logic;`
281			`signal clk100hz : std_logic;`
282			`signal clk10hz : std_logic;`
283			`signal clk1hz : std_logic;`
284
285			`signal vram_addra : std_logic_vector(15 downto 0);`
286			`signal vram_addrb : std_logic_vector(15 downto 0);`
287			`signal vram_dina : std_logic_vector(7 downto 0);`
288			`signal vram_dinb : std_logic_vector(7 downto 0);`
289			`signal vram_douta : std_logic_vector(7 downto 0);`
290			`signal vram_doutb : std_logic_vector(7 downto 0);`
291			`signal vram_wea : std_logic_VECTOR(0 downto 0) := "1";`
292			`signal vram_web : std_logic_VECTOR(0 downto 0) := "1";`
293			`signal vram_clka : std_logic;`
294			`signal vram_clkb : std_logic;`
295
296			`signal cram_addra : std_logic_vector(15 downto 0);`
297			`signal cram_addrb : std_logic_vector(15 downto 0);`
298			`signal cram_dina : std_logic_vector(7 downto 0);`
299			`signal cram_dinb : std_logic_vector(7 downto 0);`
300			`signal cram_douta : std_logic_vector(7 downto 0);`
301			`signal cram_doutb : std_logic_vector(7 downto 0);`
302			`signal cram_wea : std_logic_VECTOR(0 downto 0) := "1";`
303			`signal cram_web : std_logic_VECTOR(0 downto 0) := "1";`
304			`signal cram_clka : std_logic;`
305			`signal cram_clkb : std_logic;`
306
307			`signal vram_douta_reg: std_logic_vector(7 downto 0);`
308			`signal VID_CURSOR : std_logic_vector(15 downto 0);`
309			`signal CURSOR_X : std_logic_vector(6 downto 0);`
310			`signal CURSOR_Y : std_logic_vector(5 downto 0);`
311
312			`-- sram signals`
313			`signal sram_addr : std_logic_vector(15 downto 0);`
314			`signal sram_din : std_logic_vector(7 downto 0);`
315			`signal sram_dout : std_logic_vector(7 downto 0);`
316			`signal sram_we : std_logic_vector(0 downto 0) := "1";`
317
318			`-- LCD signals`
319			`signal lcd_wea : std_logic_VECTOR(0 downto 0) := "1";`
320			`signal lcd_addra : std_logic_vector(4 downto 0);`
321			`signal lcd_addrb : std_logic_vector(4 downto 0);`
322			`signal lcd_dina : std_logic_vector(7 downto 0);`
323			`signal lcd_doutb : std_logic_vector(7 downto 0);`
324
325			`-- VGA conversion from 4 bits to 8 bit`
326			`signal VGA_Rs,`
327			`VGA_Gs,`
328			`VGA_Bs : std_logic_vector(3 downto 0);`
329			`signal VGA_HSs,`
330			`VGA_VSs : std_logic;`
331
332			`-- PS/2 Keyboard`
333			`signal ps2_read : std_logic;`
334			`signal ps2_scan_ready : std_logic;`
335			`signal ps2_ascii_sig : std_logic_vector(7 downto 0);`
336			`signal ps2_ascii_reg1 : std_logic_vector(7 downto 0);`
337			`signal ps2_ascii_reg : std_logic_vector(7 downto 0);`
338
339			`-- Rotary Control`
340			`signal rot_dir : std_logic_vector(1 downto 0);`
341			`signal rot_dir_sig : std_logic_vector(1 downto 0);`
342
343			`signal Z80SOC_VERSION : std_logic_vector(2 downto 0); -- "000" = DE1, "001" = S3E`
344
345			`begin`
346
347			`Z80SOC_VERSION <= "001"; -- "000" = DE1, "001" = S3E`
348			`Rst_n_s <= not ROT_CENTER;`
349
350			`-- Write into VRAM`
351			`vram_addra <= VID_CURSOR when (IORQ_n = '0' and MREQ_n = '1' and A(7 downto 0) = x"90") else`
352			`A - x"4000" when (A >= x"4000" and A < x"5800");`
353			`vram_wea(0) <= '0' when ((A >= x"4000" and A < x"5800" and Wr_n = '0' and MReq_n = '0') or (Wr_n = '0' and IORQ_n = '0' and A(7 downto 0) = x"90")) else`
354			`'1';`
355			`vram_dina <= DO_CPU;`
356
357			`-- Write into char ram`
358			`cram_addra <= A - x"5800";`
359			`cram_dina <= DO_CPU;`
360			`cram_wea(0) <= '0' when (A >= x"5800" and A < x"6000" and Wr_n = '0' and MReq_n = '0') else '1';`
361
362			`-- Write into LCD video ram`
363			`lcd_addra <= A - x"FFE0";`
364			`lcd_dina <= DO_CPU;`
365			`lcd_wea(0) <= '0' when (A >= x"FFE0" and A <= x"FFFF" and Wr_n = '0' and MReq_n = '0') else '1';`
366
367			`-- Write into SRAM`
368			`sram_addr <= A - x"6000";`
369			`sram_din <= DO_CPU;`
370			`sram_we(0) <= '0' when (A >= x"6000" and A < x"FFE0" and Wr_n = '0' and MReq_n = '0') else '1';`
371
372			`DI_CPU <= ("00000" & Z80SOC_VERSION) when (Rd_n = '0' and MREQ_n = '0' and A = x"52C0") else`
373			`D_ROM when (Rd_n = '0' and MREQ_n = '0' and IORQ_n = '1' and A < x"4000") else`
374			`vram_douta when (MREQ_n = '0' and IORQ_n = '1' and Rd_n = '0' and A < x"5800") else`
375			`cram_douta when (MREQ_n = '0' and IORQ_n = '1' and Rd_n = '0' and A < x"6000") else`
376			`sram_dout when (Rd_n = '0' and MREQ_n = '0' and IORQ_n = '1' and A < x"FFE0") else`
377			`("0000" & SW) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"20") else`
378			`("0000" & KEY) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"30") else`
379			`("000000" & rot_dir) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"70") else`
380			`ps2_ascii_reg when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"80") else`
381			`("0" & CURSOR_X) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"91") else`
382			`("00" & CURSOR_Y) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"92") else`
383			`"ZZZZZZZZ";`
384
385			`-- Process to latch leds and hex displays`
386			`pinout_process: process(Clk_Z80)`
387			`variable LEDG_sig : std_logic_vector(7 downto 0);`
388			`begin`
389			`if Clk_Z80'event and Clk_Z80 = '1' then`
390			`if IORQ_n = '0' and Wr_n = '0' then`
391			`-- LEDG`
392			`if A(7 downto 0) = x"01" then`
393			`LEDG_sig := DO_CPU;`
394			`end if;`
395			`end if;`
396			`end if;`
397			`-- Latches the signals`
398			`LEDG <= LEDG_sig;`
399			`end process;`
400
401			`cursorxy: process (Clk_Z80)`
402			`variable VID_X : std_logic_vector(6 downto 0);`
403			`variable VID_Y : std_logic_vector(5 downto 0);`
404			`begin`
405			`if Clk_Z80'event and Clk_Z80 = '1' then`
406			`if (IORQ_n = '0' and MREQ_n = '1' and Wr_n = '0' and A(7 downto 0) = x"91") then`
407			`VID_X := DO_CPU(6 downto 0);`
408			`elsif (IORQ_n = '0' and MREQ_n = '1' and Wr_n = '0' and A(7 downto 0) = x"92") then`
409			`VID_Y := DO_CPU(5 downto 0);`
410			`elsif (IORQ_n = '0' and MREQ_n = '1' and Wr_n = '0' and A(7 downto 0) = x"90") then`
411			`if VID_X = vid_cols - 1 then`
412			`VID_X := "0000000";`
413			`if VID_Y = vid_lines - 1 then`
414			`VID_Y := "000000";`
415			`else`
416			`VID_Y := VID_Y + 1;`
417			`end if;`
418			`else`
419			`VID_X := VID_X + 1;`
420			`end if;`
421			`end if;`
422			`end if;`
423			`VID_CURSOR <= vram_base_addr + ( VID_X + ( VID_Y * conv_std_logic_vector(vid_cols,7)));`
424			`CURSOR_X <= VID_X;`
425			`CURSOR_Y <= VID_Y;`
426			`end process;`
427
428			`-- the following three processes deals with different clock domain signals`
429			`ps2_process1: process(CLOCK_50)`
430			`begin`
431			`if CLOCK_50'event and CLOCK_50 = '1' then`
432			`if ps2_read = '1' then`
433			`if ps2_ascii_sig /= x"FF" then`
434			`ps2_read <= '0';`
435			`ps2_ascii_reg1 <= "00000000";`
436			`end if;`
437			`elsif ps2_scan_ready = '1' then`
438			`if ps2_ascii_sig = x"FF" then`
439			`ps2_read <= '1';`
440			`else`
441			`ps2_ascii_reg1 <= ps2_ascii_sig;`
442			`end if;`
443			`end if;`
444			`end if;`
445			`end process;`
446
447			`ps2_process2: process(Clk_Z80)`
448			`variable stack : std_logic_vector(15 downto 0):=x"7FDE";`
449			`begin`
450			`if Clk_Z80'event and Clk_Z80 = '1' then`
451			`ps2_ascii_reg <= ps2_ascii_reg1;`
452			`end if;`
453			`end process;`
454
455			`rot_process: process(clk100hz)`
456			`begin`
457			`if clk100hz'event and clk100hz = '1' then`
458			`rot_dir <= rot_dir_sig;`
459			`end if;`
460			`end process;`
461
462			`One <= '1';`
463			`z80_inst: T80se`
464			`port map (`
465			`M1_n => open,`
466			`MREQ_n => MReq_n,`
467			`IORQ_n => IORq_n,`
468			`RD_n => Rd_n,`
469			`WR_n => Wr_n,`
470			`RFSH_n => open,`
471			`HALT_n => open,`
472			`WAIT_n => One,`
473			`INT_n => One,`
474			`NMI_n => One,`
475			`RESET_n => Rst_n_s,`
476			`BUSRQ_n => One,`
477			`BUSAK_n => open,`
478			`CLK_n => Clk_Z80,`
479			`CLKEN => One,`
480			`A => A,`
481			`DI => DI_CPU,`
482			`DO => DO_CPU`
483			`);`
484
485			`ps2_kbd_inst : ps2kbd PORT MAP (`
486			`keyboard_clk => PS2_CLK,`
487			`keyboard_data => PS2_DAT,`
488			`clock => CLOCK_50,`
489			`clkdelay => clk100hz,`
490			`reset => Rst_n_s,`
491			`read => ps2_read,`
492			`scan_ready => ps2_scan_ready,`
493			`ps2_ascii_code => ps2_ascii_sig`
494			`);`
495
496			`clk25mhz_proc: process (CLOCK_50)`
497			`begin`
498			`if CLOCK_50'event and CLOCK_50 = '1' then`
499			`clk25mhz <= not clk25mhz;`
500			`end if;`
501			`end process;`
502
503			`clkdiv_inst: clk_div`
504			`port map (`
505			`clock_25Mhz => clk25mhz,`
506			`clock_1MHz => open,`
507			`clock_100KHz => open,`
508			`clock_10KHz => open,`
509			`clock_1KHz => open,`
510			`clock_100Hz => clk100hz,`
511			`clock_10Hz => clk10hz,`
512			`clock_1Hz => clk1hz`
513			`);`
514
515			`clock_z80_inst : Clock_357Mhz`
516			`port map (`
517			`clock_50Mhz => CLOCK_50,`
518			`clock_357Mhz => Clk_Z80`
519			`);`
520
521			`lcd_inst: lcd`
522			`port map (`
523			`clk => CLOCK_50,`
524			`reset => not Rst_n_s,`
525			`SF_D => SF_D,`
526			`LCD_E => LCD_E,`
527			`LCD_RS => LCD_RS,`
528			`LCD_RW => LCD_RW,`
529			`SF_CE0 => SF_CE0,`
530			`lcd_addr => lcd_addrb,`
531			`lcd_char => lcd_doutb`
532			`);`
533
534			`video_inst: video port map (`
535			`CLOCK_25 => clk25mhz,`
536			`VRAM_DATA => vram_doutb,`
537			`VRAM_ADDR => vram_addrb(12 downto 0),`
538			`VRAM_CLOCK => vram_clkb,`
539			`VRAM_WREN => vram_web,`
540			`CRAM_DATA => cram_doutb,`
541			`CRAM_ADDR => cram_addrb(10 downto 0),`
542			`CRAM_WEB => cram_web,`
543			`VGA_R => VGA_R,`
544			`VGA_G => VGA_G,`
545			`VGA_B => VGA_B,`
546			`VGA_HS => VGA_HS,`
547			`VGA_VS => VGA_VS`
548			`);`
549
550			`vram_inst : vram`
551			`port map (`
552			`addra => vram_addra(12 downto 0),`
553			`addrb => vram_addrb(12 downto 0),`
554			`clka => Clk_Z80,`
555			`clkb => vram_clkb,`
556			`dina => vram_dina,`
557			`dinb => vram_dinb,`
558			`douta => vram_douta,`
559			`doutb => vram_doutb,`
560			`wea => NOT vram_wea,`
561			`web => NOT vram_web);`
562
563			`cram: charram2k`
564			`port map (`
565			`addra => cram_addra(10 downto 0),`
566			`addrb => cram_addrb(10 downto 0),`
567			`clka => Clk_Z80,`
568			`clkb => vram_clkb,`
569			`dina => cram_dina,`
570			`dinb => cram_dinb,`
571			`douta => cram_douta,`
572			`doutb => cram_doutb,`
573			`wea => NOT cram_wea,`
574			`web => NOT cram_web);`
575
576			`lcdvram_inst : lcdvram`
577			`port map (`
578			`addra => lcd_addra,`
579			`addrb => lcd_addrb,`
580			`clka => Clk_Z80,`
581			`clkb => CLOCK_50,`
582			`dina => lcd_dina,`
583			`doutb => lcd_doutb,`
584			`wea => NOT lcd_wea`
585			`);`
586
587			`rom_inst : rom`
588			`port map (`
589			`clka => Clk_Z80,`
590			`addra => A(13 downto 0),`
591			`douta => D_ROM`
592			`);`
593
594			`ram_inst : ram`
595			`port map (`
596			`clka => Clk_Z80,`
597			`dina => sram_din,`
598			`addra => sram_addr(13 downto 0),`
599			`wea => NOT sram_we,`
600			`douta => sram_dout);`
601
602			`rotary_inst : ROT_CTRL`
603			`port map (`
604			`CLOCK => CLOCK_50,`
605			`ROT_A => ROT_A,`
606			`ROT_B => ROT_B,`
607			`DIRECTION => rot_dir_sig`
608			`);`
609
610			`end;`
611