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Subversion Repositories z80soc

[/] [z80soc/] [trunk/] [V0.7.1a/] [rom/] [rom_xlib.vhd] - Blame information for rev 42

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Line No. Rev Author Line
1 41 rrred
library IEEE;
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use  IEEE.STD_LOGIC_1164.all;
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use  IEEE.STD_LOGIC_ARITH.all;
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use  IEEE.STD_LOGIC_UNSIGNED.all;
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Library XilinxCoreLib;
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ENTITY charrom IS
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        port (
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        clk             : IN    STD_LOGIC;
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                        character_address                       : IN    STD_LOGIC_VECTOR(7 DOWNTO 0);
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                        font_row, font_col                      : IN    STD_LOGIC_VECTOR(2 DOWNTO 0);
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                        rom_mux_output  : OUT   STD_LOGIC);
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END charrom;
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ARCHITECTURE charrom_a OF charrom IS
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        SIGNAL  dout: STD_LOGIC_VECTOR(7 DOWNTO 0);
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        SIGNAL  addr: STD_LOGIC_VECTOR(10 DOWNTO 0);
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component char
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        port (
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        clka: IN std_logic;
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        addra: IN std_logic_VECTOR(10 downto 0);
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        douta: OUT std_logic_VECTOR(7 downto 0));
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end component;
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BEGIN
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addr <= character_address & font_row;
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-- Mux to pick off correct rom data bit from 8-bit word
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-- for on screen character generation
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rom_mux_output <= dout ( (CONV_INTEGER(NOT font_col(2 downto 0))));
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char_inst : char
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                port map (
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                        addra => addr,
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                        clka => clk,
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                        douta => dout);
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END charrom_a;
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