Subversion Repositories z80soc

--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_DECODES=4 LPM_WIDTH=2 data enable eq

--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ  VERSION_END

-- Copyright (C) 1991-2013 Altera Corporation

--  Your use of Altera Corporation's design tools, logic functions

--  and other software and tools, and its AMPP partner logic

--  functions, and any output files from any of the foregoing

--  (including device programming or simulation files), and any

--  associated documentation or information are expressly subject

--  to the terms and conditions of the Altera Program License

--  Subscription Agreement, Altera MegaCore Function License

--  Agreement, or other applicable license agreement, including,

--  without limitation, that your use is for the sole purpose of

--  programming logic devices manufactured by Altera and sold by

--  Altera or its authorized distributors.  Please refer to the

--  applicable agreement for further details.

--synthesis_resources = lut 4

SUBDESIGN decode_4oa

(

        data[1..0]      :       input;

        enable  :       input;

        eq[3..0]        :       output;

)

VARIABLE

        data_wire[1..0] : WIRE;

        enable_wire     : WIRE;

        eq_node[3..0]   : WIRE;

        eq_wire[3..0]   : WIRE;

        w_anode141w[2..0]       : WIRE;

        w_anode154w[2..0]       : WIRE;

        w_anode162w[2..0]       : WIRE;

        w_anode170w[2..0]       : WIRE;

BEGIN

        data_wire[] = data[];

        enable_wire = enable;

        eq[] = eq_node[];

        eq_node[3..0] = eq_wire[3..0];

        eq_wire[] = ( w_anode170w[2..2], w_anode162w[2..2], w_anode154w[2..2], w_anode141w[2..2]);

        w_anode141w[] = ( (w_anode141w[1..1] & (! data_wire[1..1])), (w_anode141w[0..0] & (! data_wire[0..0])), enable_wire);

        w_anode154w[] = ( (w_anode154w[1..1] & (! data_wire[1..1])), (w_anode154w[0..0] & data_wire[0..0]), enable_wire);

        w_anode162w[] = ( (w_anode162w[1..1] & data_wire[1..1]), (w_anode162w[0..0] & (! data_wire[0..0])), enable_wire);

        w_anode170w[] = ( (w_anode170w[1..1] & data_wire[1..1]), (w_anode170w[0..0] & data_wire[0..0]), enable_wire);

END;

--VALID FILE