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rrred |
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-- This design is part of:
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-- Z80SoC (Z80 System on Chip)
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-- Ronivon Candido Costa
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-- ronivon.costa@gmail.com
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--
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-- 2010 - 11 - 22
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-- Fixed bug in video to allow resolutions up to 80x60
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--
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-- 2010 - 02 - 17 Update
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-- Changed the entity to include signals for the char memory
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-- The char memory is a dual port ram memory, and now
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-- the char paterns can be modified by software.
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--
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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ENTITY video is
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PORT( CLOCK_25 : IN STD_LOGIC;
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VRAM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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VRAM_ADDR : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
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VRAM_CLOCK : OUT STD_LOGIC;
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VRAM_WREN : OUT STD_LOGIC;
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CRAM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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CRAM_ADDR : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
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CRAM_WEB : OUT STD_LOGIC;
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VGA_R,
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VGA_G,
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VGA_B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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VGA_HS,
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VGA_VS : OUT STD_LOGIC);
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END video;
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ARCHITECTURE A OF video IS
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use work.z80soc_pack.all;
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-- Added for VDU support
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constant vid_width : std_logic_vector := "001010000"; -- 80 columns
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signal Clock_video : std_logic;
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signal VGA_R_sig : std_logic_vector(3 downto 0);
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signal VGA_G_sig : std_logic_vector(3 downto 0);
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signal VGA_B_sig : std_logic_vector(3 downto 0);
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signal pixel_row_sig : std_logic_vector(9 downto 0);
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signal pixel_column_sig : std_logic_vector(9 downto 0);
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signal pixel_clock_sig : std_logic;
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signal char_addr_sig : std_logic_vector(7 downto 0);
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signal font_row_sig : std_logic_vector(2 downto 0);
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signal font_col_sig : std_logic_vector(2 downto 0);
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signal pixel_sig : std_logic;
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signal video_on_sig : std_logic;
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constant sv1 : integer := 3 + pixelsxchar - 1;
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constant sv2 : integer := 9 + pixelsxchar - 1;
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constant cv1 : integer := 0 + pixelsxchar - 1;
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constant cv2 : integer := 2 + pixelsxchar - 1;
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signal fix : integer;
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COMPONENT VGA_SYNC
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PORT( clock_25Mhz : IN STD_LOGIC;
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red, green, blue : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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red_out, green_out, blue_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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horiz_sync_out, vert_sync_out,
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video_on, pixel_clock : OUT STD_LOGIC;
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pixel_row, pixel_column : OUT STD_LOGIC_VECTOR(9 DOWNTO 0));
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END COMPONENT;
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BEGIN
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VGA_R_sig <= "0000";
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VGA_G_sig <= "0000";
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VGA_B_sig <= pixel_sig & pixel_sig & pixel_sig & pixel_sig;
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-- Fonts ROM read
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-- Picks next letter for a 80 Columns x 30 Lines display
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VRAM_WREN <= '1';
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VRAM_CLOCK <= pixel_clock_sig;
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VRAM_ADDR <= pixel_row_sig(sv2 downto sv1) * conv_std_logic_vector(vid_cols,7) + pixel_column_sig(sv2 downto sv1);
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-- Fonts RAM read
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-- Takes the letter, calculates the position in the char memory to get the pixel pattern
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-- Plot the pixel in the video
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-- Using pixel_row(3 downto 1) has the effect of "shifting" (multiplying by 2)
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-- This will plot 2 pixels on video for every pixel defined on char memory
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CRAM_WEB <= '1';
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CRAM_ADDR <= VRAM_DATA & pixel_row_sig(cv2 downto cv1);
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fix <= 1 when pixelsxchar = 2 else 2;
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pixel_sig <= CRAM_DATA (CONV_INTEGER(NOT (pixel_column_sig(cv2 downto cv1) - fix))) when
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( (pixel_row_sig < (pixelsxchar * 8 * vid_lines)) and (pixel_column_sig < (pixelsxchar * 8 * vid_cols)) ) else
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'0';
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vga_sync_inst: VGA_SYNC
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port map (
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clock_25Mhz => CLOCK_25,
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red => VGA_R_sig,
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green => VGA_G_sig,
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blue => VGA_B_sig,
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red_out => VGA_R,
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green_out => VGA_G,
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blue_out => VGA_B,
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horiz_sync_out => VGA_HS,
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vert_sync_out => VGA_VS,
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video_on => video_on_sig,
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pixel_clock => pixel_clock_sig,
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pixel_row => pixel_row_sig,
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pixel_column => pixel_column_sig
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);
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END A;
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