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https://opencores.org/ocsvn/z80soc/z80soc/trunk
[/] [z80soc/] [trunk/] [V0.7.3/] [DE1/] [vhdl/] [z80soc_pack.vhd.bak] - Blame information for rev 46
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rrred |
-------------------------------------------------------------------------------------------------
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-- This design is part of:
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-- Z80SoC (Z80 System on Chip)
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-- Ronivon Candido Costa
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-- ronivon.costa@gmail.com
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--
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library ieee;
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use ieee.std_logic_1164.all;
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package z80soc_pack is
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constant Z80SOC_Arch_value : std_logic_vector(2 downto 0) := "010"; -- 0 = DE1, 1 = S3E, 2 = DE2
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-- Generic constrainsts
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constant vid_cols : integer := 80; -- video number of columns
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constant vid_lines : integer := 60; -- video number of lines
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constant pixelsxchar : integer := 1;
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constant Z80SOC_Arch_addr : std_logic_vector(15 downto 0) := x"57DF";
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constant KEYPRESS_addr : std_logic_vector(15 downto 0) := x"57DE";
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constant LCD_addr : std_logic_vector(15 downto 0) := x"57DC";
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constant RAMTOP_addr : std_logic_vector(15 downto 0) := x"57DA";
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constant RAMBOTT_addr : std_logic_vector(15 downto 0) := x"57D8";
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constant CHARRAM_addr : std_logic_vector(15 downto 0) := x"57D6";
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constant VRAM_addr : std_logic_vector(15 downto 0) := x"57D4";
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constant STACK_addr : std_logic_vector(15 downto 0) := x"57D2";
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-- DE1
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--constant SRAM_width : integer := 17;
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--constant RAMTOP_value : std_logic_vector(15 downto 0) := x"8FFF";
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-- DE2-115
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constant SRAM_width : integer := 19;
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constant LCD_value : std_logic_vector(15 downto 0) := x"57E0";
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constant RAMTOP_value : std_logic_vector(15 downto 0) := x"FFFF";
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constant RAMBOTT_value : std_logic_vector(15 downto 0) := x"6000";
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constant VRAM_value : std_logic_vector(15 downto 0) := x"4000";
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constant CHARRAM_value : std_logic_vector(15 downto 0) := x"5800";
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constant STACK_value : std_logic_vector(15 downto 0) := x"FFFF";
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end z80soc_pack;
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