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[/] [z80soc/] [trunk/] [V0.7.3/] [DE2115/] [vhdl/] [z80soc.vhd] - Blame information for rev 46

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Line No. Rev Author Line
1 46 rrred 
-------------------------------------------------------------------------------------------------
2 
-- Z80SoC (Z80 System on Chip)
3 
-- Ronivon Candido Costa
4 
-- ronivon.costa@gmail.com
5 
--
6 
-- Version history:
7 
-------------------
8 
-- version 0.7.1
9 
-- 2010 / 11 / 22
10 
-- Change memory layout and increased Rom, using Megawizard plug in manager
11 
-- Memory cores redefined
12 
-- Fixed bug in the video.vhd
13 
-- New rom demo in C (SDCC)
14 
--
15 
-- version 0.7
16 
-- Release Date: 2010 / 02 / 17
17 
-- version 0.6 for for Altera DE1
18 
-- Release Date: 2008 / 05 / 21
19 
--
20 
-- Version 0.5 Beta for Altera DE1
21 
-- Developer: Ronivon Candido Costa
22 
-- Release Date: 2008 / 04 / 16
23 
--
24 
-- Based on the T80 core: http://www.opencores.org/projects.cgi/web/t80
25 
-- This version developed and tested on: Altera DE1 Development Board
26 
--
27 
-- Peripherals configured (Using Ports):
28 
--
29 
--  16 KB Internal ROM  Read        (0x0000h - 0x3FFFh)
30 
--  08 KB INTERNAL VRAM Write       (0x4000h - 0x5FFFh)
31 
--  32 KB External SRAM Read/Write  (0x8000h - 0xFFFFh)
32 
--  08 Green Leds       Out     (Port 0x01h)
33 
--  08 Red Leds         Out     (Port 0x02h)
34 
--  04 Seven Seg displays   Out     (Ports 0x11h and 0x10h)
35 
--  36 Pins GPIO0       In/Out  (Ports 0xA0h, 0xA1h, 0xA2h, 0xA3h, 0xA4h, 0xC0h)
36 
--  36 Pins GPIO1       In/Out  (Ports 0xB0h, 0xB1h, 0xB2h, 0xB3h, 0xB4h, 0xC1h)
37 
--  08 Switches         In      (Port 0x20h)
38 
--  04 Push buttons     In      (Port 0x30h)
39 
--  01 PS/2 keyboard        In      (Port 0x80h)
40 
--  01 Video write port In      (Port 0x90h)
41 
--
42 
--  Revision history:
43 
--
44 
-- 2008/05/23 - Modified RAM layout to support new and future improvements
45 
--            - Added port 0x90 to write a character to video.
46 
--            - Cursor x,y automatically updated after writing to port 0x90
47 
--            - Added port 0x91 for video cursor X
48 
--            - Added port 0x92 for video cursor Y
49 
--            - Updated ROM to demonstrate how to use these new resources
50 
--            - Changed ROM to support 14 bit addresses (16 Kb)
51 
--
52 
-- 2008/05/12 - Added support for the Rotary Knob
53 
--            - ROT_CENTER push button (Knob) reserved for RESET
54 
--            - The four push buttons are now available for the user (Port 0x30)
55 
--
56 
-- 2008/05/11 - Fixed access to RAM and VRAM,
57 
--              Released same ROM version for DE1 and S3E
58 
--
59 
-- 2008/05/01 - Added LCD support for Spartan 3E
60 
--
61 
-- 2008/04(21 - Release of Version 0.5-S3E-Beta for Diligent Spartan 3E
62 
--
63 
--  2008/04/17 - Added Video support for 40x30 mode
64 
--
65 
-- 2008/04/16 - Release of Version 0.5-DE1-Beta for Altera DE1
66 
--
67 
-- TO-DO:
68 
-- - Implement hardware control for the A/D and IO pins
69 
-- - Monitor program to introduce Z80 Assmebly codes and run
70 
-- - Serial communication, to download assembly code from PC
71 
-- - Add hardware support for 80x40 Video out
72 
-- - SD/MMC card interface to read/store data and programs
73 
-------------------------------------------------------------------------------------------------
74 
 
75 
library IEEE;
76 
use IEEE.std_logic_1164.all;
77 
use IEEE.std_logic_arith.all;
78 
use IEEE.std_logic_unsigned.all;
79 
use work.z80soc_pack.all;
80 
 
81 
entity  Z80SOC is
82 
    port(
83 
    CLOCK_50                    : in std_logic;
84 
    KEY                         : in std_logic_vector(3 downto 0);
85 
    SW                          : in std_logic_vector(17 downto 0);
86 
    HEX0                        : out std_logic_vector(6 downto 0);
87 
    HEX1                        : out std_logic_vector(6 downto 0);
88 
    HEX2                        : out std_logic_vector(6 downto 0);
89 
    HEX3                        : out std_logic_vector(6 downto 0);
90 
    HEX4                        : out std_logic_vector(6 downto 0);
91 
    HEX5                        : out std_logic_vector(6 downto 0);
92 
    HEX6                        : out std_logic_vector(6 downto 0);
93 
    HEX7                        : out std_logic_vector(6 downto 0);
94 
    LEDG                        : out std_logic_vector(8 downto 0);    -- Green LEDs
95 
    LEDR                        : out std_logic_vector(17 downto 0);   -- Red LEDs
96 
 
97 
    -- UART
98 
    UART_TXD                    : out std_logic;                       -- UART transmitter
99 
    UART_RXD                    : in std_logic;                        -- UART receiver
100 
    UART_RTS                    : in std_logic;                        -- UART RTS
101 
    UART_CTS                    : in std_logic;                        -- UART CTS
102 
 
103 
    -- SDRAM
104 
    DRAM_BA_0                   : out std_logic;                       -- Bank Address 0
105 
    DRAM_BA_1                   : out std_logic;                       -- Bank Address 1
106 
    DRAM_DQM_0                  : out std_logic;                       -- Byte Data Mask 0
107 
    DRAM_DQM_1                  : out std_logic;                       -- Byte Data Mask 1
108 
    DRAM_DQM_2                  : out std_logic;                       -- Byte Data Mask 2
109 
    DRAM_DQM_3                  : out std_logic;                       -- Byte Data Mask 3
110 
    DRAM_WE_N                   : out std_logic;
111 
    DRAM_CAS_N                  : out std_logic;                       -- Column Address
112 
    DRAM_RAS_N                  : out std_logic;                       -- Row Address Strobe
113 
    DRAM_CS_N                   : out std_logic;                       -- Chip Select
114 
    DRAM_DQ                     : inout std_logic_vector(31 downto 0); -- Data Bus
115 
    DRAM_ADDR                   : out std_logic_vector(12 downto 0);   -- Address Bus
116 
    DRAM_CLK                    : out std_logic;                       -- Clock
117 
    DRAM_CKE                    : out std_logic;                       -- Clock Enable
118 
 
119 
    -- FLASH
120 
    FL_DQ                       : inout std_logic_vector(7 downto 0);  -- Data bus
121 
    FL_ADDR                     : out std_logic_vector(22 downto 0);   -- Address bus
122 
    FL_RY                       : in std_logic;
123 
    FL_WP_N                     : out std_logic;
124 
    FL_WE_N                     : out std_logic;                       -- Write Enable
125 
    FL_RST_N                    : out std_logic;                       -- Reset
126 
    FL_OE_N                     : out std_logic;                       -- Output Enable
127 
    FL_CE_N                     : out std_logic;                       -- Chip Enable
128 
 
129 
    -- SRAM
130 
    SRAM_DQ                     : inout std_logic_vector(15 downto 0); -- Data bus 16 Bits
131 
    SRAM_ADDR                   : out std_logic_vector(SRAM_width - 1 downto 0); -- Address bus 18 Bits
132 
    SRAM_UB_N                   : out std_logic;                       -- High-byte Data Mask
133 
    SRAM_LB_N                   : out std_logic;                       -- Low-byte Data Mask
134 
    SRAM_WE_N                   : out std_logic;                       -- Write Enable
135 
    SRAM_CE_N                   : out std_logic;                       -- Chip Enable
136 
    SRAM_OE_N                   : out std_logic;                       -- Output Enable
137 
 
138 
    -- SD card interface
139 
    SD_DAT0                     : in std_logic;                        -- SD Card Data      SD "DAT 0/DataOut"
140 
    SD_DAT1                     : inout std_logic;                     -- SD Card Data   SD "DAT 1"
141 
    SD_DAT2                     : inout std_logic;                     -- SD Card Data 3   SD "DAT 2"
142 
    SD_DAT3                     : out std_logic;                       -- SD Card Data 3    SD "DAT 3/nCS"
143 
    SD_CMD                      : out std_logic;                       -- SD Card Command   SD "CMD/DataIn"
144 
    SD_CLK                      : out std_logic;                       -- SD Card Clock     SD "CLK"
145 
 
146 
    -- PS/2 port
147 
    PS2_DAT                     : inout std_logic;                     -- Data
148 
    PS2_CLK                     : inout std_logic;                     -- Clock
149 
    PS2_DAT2                    : inout std_logic;                     -- Data
150 
    PS2_CLK2                    : inout std_logic;                     -- Clock
151 
 
152 
    -- VGA output
153 
    VGA_SYNC_N                  : out std_logic;
154 
    VGA_CLK                     : out std_logic;
155 
    VGA_BLANK_N                 : out std_logic;
156 
    VGA_HS                      : out std_logic;                       -- H_SYNC
157 
    VGA_VS                      : out std_logic;                       -- SYNC
158 
    VGA_R                       : out std_logic_vector(7 downto 0);    -- Red[7:0]
159 
    VGA_G                       : out std_logic_vector(7 downto 0);    -- Green[7:0]
160 
    VGA_B                       : out std_logic_vector(7 downto 0);    -- Blue[7:0]
161 
 
162 
    -- Audio CODEC
163 
    AUD_ADCLRCK                 : inout std_logic;                     -- ADC LR Clock
164 
    AUD_ADCDAT                  : in std_logic;                        -- ADC Data
165 
    AUD_DACLRCK                 : inout std_logic;                     -- DAC LR Clock
166 
    AUD_DACDAT                  : out std_logic;                       -- DAC Data
167 
    AUD_BCLK                    : inout std_logic;                     -- Bit-Stream Clock
168 
    AUD_XCK                     : out std_logic;                       -- Chip Clock
169 
 
170 
        -- LCD
171 
    LCD_RS                      : out std_logic;
172 
    LCD_EN                      : out std_logic;
173 
    LCD_RW                      : out std_logic;
174 
    LCD_ON                      : out std_logic;
175 
    LCD_BLON                    : out std_logic; -- lcd on de2 do not support this signal
176 
    LCD_DATA                    : inout std_logic_vector(7 downto 0));
177 
end Z80SOC;
178 
 
179 
architecture rtl of Z80SOC is
180 
 
181 
    component T80se
182 
    generic(
183 
        Mode                    : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
184 
        T2Write                 : integer := 1; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
185 
        IOWait                  : integer := 1  -- 0 => Siomngle cycle I/O, 1 => Std I/O cycle
186 
    );
187 
    port(
188 
        RESET_n                 : in std_logic;
189 
        CLK_n                   : in std_logic;
190 
        CLKEN                   : in std_logic;
191 
        WAIT_n                  : in std_logic;
192 
        INT_n                   : in std_logic;
193 
        NMI_n                   : in std_logic;
194 
        BUSRQ_n                 : in std_logic;
195 
        M1_n                    : out std_logic;
196 
        MREQ_n                  : out std_logic;
197 
        IORQ_n                  : out std_logic;
198 
        RD_n                    : out std_logic;
199 
        WR_n                    : out std_logic;
200 
        RFSH_n                  : out std_logic;
201 
        HALT_n                  : out std_logic;
202 
        BUSAK_n                 : out std_logic;
203 
        A                       : out std_logic_vector(15 downto 0);
204 
        DI                      : in std_logic_vector(7 downto 0);
205 
        DO                      : out std_logic_vector(7 downto 0)
206 
    );
207 
    end component;
208 
 
209 
    component rom
210 
    port (
211 
        clock                   : in std_logic;
212 
        address                 : in std_logic_vector(13 downto 0);
213 
        q                       : out std_logic_vector(7 downto 0));
214 
    end component;
215 
 
216 
    component clk_div
217 
    PORT
218 
    (
219 
        clock_in_50Mhz          : in    std_logic;
220 
        clock_25MHz             : out   std_logic;
221 
        clock_10MHz             : out   std_logic;
222 
        clock_357MHz            : out   std_logic;
223 
        clock_1MHz              : out   std_logic;
224 
        clock_100KHz            : out   std_logic;
225 
        clock_10KHz             : out   std_logic;
226 
        clock_1KHz              : out   std_logic;
227 
        clock_100Hz             : out   std_logic;
228 
        clock_10Hz              : out   std_logic;
229 
        clock_1Hz               : out   std_logic);
230 
    end component;
231 
 
232 
    component decoder_7seg
233 
    port (
234 
        NUMBER                  : in   std_logic_vector(3 downto 0);
235 
        HEX_DISP                : out  std_logic_vector(6 downto 0));
236 
    end component;
237 
 
238 
    component ps2kbd
239 
    port (
240 
        keyboard_clk            : inout std_logic;
241 
        keyboard_data           : inout std_logic;
242 
        clock                   : in std_logic;
243 
        clkdelay                : in std_logic;
244 
        reset                   : in std_logic;
245 
        read                    : in std_logic;
246 
        scan_ready              : out std_logic;
247 
        ps2_ascii_code          : out std_logic_vector(7 downto 0));
248 
    end component;
249 
 
250 
    component vram
251 
    port
252 
    (
253 
        rdaddress               : in std_logic_vector (12 downto 0);
254 
        wraddress               : in std_logic_vector (12 downto 0);
255 
        rdclock                 : in std_logic;
256 
        wrclock                 : in std_logic;
257 
        data                    : in std_logic_vector (7 downto 0);
258 
        wren                    : in std_logic;
259 
        q                       : out std_logic_vector (7 downto 0)
260 
    );
261 
    end component;
262 
 
263 
    component charram
264 
    port (
265 
        data                    : in std_logic_vector (7 downto 0);
266 
        rdaddress               : in std_logic_vector (10 downto 0);
267 
        rdclock                 : in std_logic ;
268 
        wraddress               : in std_logic_vector (10 downto 0);
269 
        wrclock                 : in std_logic;
270 
        wren                    : in std_logic;
271 
        q                       : out std_logic_vector (7 downto 0));
272 
    end component;
273 
 
274 
    COMPONENT video
275 
    PORT (
276 
        CLOCK_25                : in std_logic;
277 
        VRAM_DATA               : in std_logic_vector(7 downto 0);
278 
        VRAM_ADDR               : out std_logic_vector(13 downto 0);
279 
        VRAM_CLOCK              : out std_logic;
280 
        VRAM_WREN               : out std_logic;
281 
        CRAM_DATA               : in std_logic_vector(7 downto 0);
282 
        CRAM_ADDR               : out std_logic_vector(10 downto 0);
283 
        CRAM_WEB                : out std_logic;
284 
        VGA_R                   : out std_logic_vector(3 downto 0);
285 
        VGA_G                   : out std_logic_vector(3 downto 0);
286 
        VGA_B                   : out std_logic_vector(3 downto 0);
287 
        VGA_HS                  : out std_logic;
288 
        VGA_VS                  : out std_logic);
289 
    END COMPONENT;
290 
 
291 
    COMPONENT LCD
292 
    PORT(
293 
        reset                   : in     std_logic;  -- map this port to a Switch
294 
                                                             -- within your [port declarations / Pin Planer]
295 
        CLOCK_50                : in     std_logic;  -- using the de2 50mhz Clk,
296 
                                                             -- in order to genreate the 400Hz signal...
297 
                                                       -- clk_count_400hz reset count value must be set to:  <= x"0F424"
298 
        LCD_RS                  : out std_logic;
299 
        LCD_EN                  : out std_logic;
300 
        LCD_RW                  : out std_logic;
301 
        LCD_ON                  : out std_logic;
302 
        LCD_BLON                : out std_logic;
303 
        LCD_DATA                : inout std_logic_vector(7 downto 0);
304 
        lcd_on_sig              : in std_logic;
305 
        next_char               : in std_logic_vector(7 downto 0);
306 
        char_count              : out std_logic_vector(4 downto 0);
307 
        clk400hz                : out std_logic);
308 
    END COMPONENT;
309 
 
310 
    signal MREQ_n               : std_logic;
311 
    signal IORQ_n               : std_logic;
312 
    signal RD_n                 : std_logic;
313 
    signal WR_n                 : std_logic;
314 
    signal MWr_n                : std_logic;
315 
    signal Rst_n_s              : std_logic;
316 
    signal Clk_Z80              : std_logic;
317 
    signal DI_CPU               : std_logic_vector(7 downto 0);
318 
    signal DO_CPU               : std_logic_vector(7 downto 0);
319 
    signal A                    : std_logic_vector(15 downto 0);
320 
    signal One                  : std_logic;
321 
 
322 
    signal D_ROM                : std_logic_vector(7 downto 0);
323 
    signal rom_data             : std_logic_vector(7 downto 0);
324 
    signal rom_wren             : std_logic;
325 
 
326 
    signal clk_count_400hz      : std_logic_vector(19 downto 0);
327 
    signal clk100mhz            : std_logic;
328 
    signal clk25mhz             : std_logic;
329 
    signal clk1mhz              : std_logic;
330 
    signal clk10mhz             : std_logic;
331 
    signal clk400hz             : std_logic;
332 
    signal clk100hz             : std_logic;
333 
    signal clk10hz              : std_logic;
334 
    signal clk1hz               : std_logic;
335 
    signal clk357mhz            : std_logic;
336 
    signal clk1khz              : std_logic;
337 
 
338 
    signal HEX_DISP0            : std_logic_vector(6 downto 0);
339 
    signal HEX_DISP1            : std_logic_vector(6 downto 0);
340 
    signal HEX_DISP2            : std_logic_vector(6 downto 0);
341 
    signal HEX_DISP3            : std_logic_vector(6 downto 0);
342 
    signal HEX_DISP4            : std_logic_vector(6 downto 0);
343 
    signal HEX_DISP5            : std_logic_vector(6 downto 0);
344 
    signal HEX_DISP6            : std_logic_vector(6 downto 0);
345 
    signal HEX_DISP7            : std_logic_vector(6 downto 0);
346 
 
347 
    signal NUMBER0              : std_logic_vector(3 downto 0);
348 
    signal NUMBER1              : std_logic_vector(3 downto 0);
349 
    signal NUMBER2              : std_logic_vector(3 downto 0);
350 
    signal NUMBER3              : std_logic_vector(3 downto 0);
351 
    signal NUMBER4              : std_logic_vector(3 downto 0);
352 
    signal NUMBER5              : std_logic_vector(3 downto 0);
353 
    signal NUMBER6              : std_logic_vector(3 downto 0);
354 
    signal NUMBER7              : std_logic_vector(3 downto 0);
355 
 
356 
    signal  vram_addra          : std_logic_vector(15 downto 0);
357 
    signal  vram_addrb          : std_logic_vector(13 downto 0);
358 
    signal  vram_dina           : std_logic_vector(7 downto 0);
359 
    signal  vram_dinb           : std_logic_vector(7 downto 0);
360 
    signal  vram_douta          : std_logic_vector(7 downto 0);
361 
    signal  vram_doutb          : std_logic_vector(7 downto 0);
362 
    signal  vram_wea            : std_logic; --_vector(0 downto 0);
363 
    signal  vram_web            : std_logic; --_vector(0 downto 0);
364 
    signal  vram_clka           : std_logic;
365 
    signal  vram_clkb           : std_logic;
366 
 
367 
    signal cram_addra           : std_logic_vector(15 downto 0);
368 
    signal cram_addrb           : std_logic_vector(15 downto 0);
369 
    signal cram_dina            : std_logic_vector(7 downto 0);
370 
    signal cram_dinb            : std_logic_vector(7 downto 0);
371 
    signal cram_douta           : std_logic_vector(7 downto 0);
372 
    signal cram_doutb           : std_logic_vector(7 downto 0);
373 
    signal cram_wea             : std_logic;
374 
    signal cram_web             : std_logic;
375 
    signal cram_clka            : std_logic;
376 
    signal cram_clkb            : std_logic;
377 
 
378 
    -- PS/2 Keyboard
379 
    signal ps2_read             : std_logic;
380 
    signal ps2_scan_ready       : std_logic;
381 
    signal ps2_ascii_sig        : std_logic_vector(7 downto 0);
382 
    signal ps2_ascii_reg1       : std_logic_vector(7 downto 0);
383 
    signal ps2_ascii_reg        : std_logic_vector(7 downto 0);
384 
 
385 
    -- LCD signals
386 
    type character_string is array ( 0 to 31 ) of STD_LOGIC_VECTOR( 7 downto 0 );
387 
 
388 
    signal lcdvram              : character_string;
389 
    signal lcdaddr_w_sig        : std_logic_vector(15 downto 0);
390 
    signal lcdaddr_sig          : std_logic_vector(15 downto 0) := LCD_value;
391 
    signal char_count_sig       : std_logic_vector(4 downto 0);
392 
    signal next_char_sig        : std_logic_vector(7 downto 0);
393 
    signal temp                 : std_logic;
394 
 
395 
    signal Z80SOC_Arch_reg      : std_logic_vector(2 downto 0)  := Z80SOC_Arch_value;
396 
                                      -- "000" = DE1, "001" = S3E, "010" = DE2115
397 
    signal RAMTOP_reg           : std_logic_vector(15 downto 0) := RAMTOP_value;
398 
    signal RAMBOTT_reg          : std_logic_vector(15 downto 0) := RAMBOTT_value;
399 
    signal LCD_reg              : std_logic_vector(15 downto 0) := LCD_value;
400 
    signal VRAM_reg             : std_logic_vector(15 downto 0) := VRAM_value;
401 
    signal STACK_reg            : std_logic_vector(15 downto 0) := STACK_value;
402 
    signal CHARRAM_reg          : std_logic_vector(15 downto 0) := CHARRAM_value;
403 
    signal VIDCOLS_reg          : std_logic_vector(7 downto 0)  := conv_std_logic_vector(vid_cols, 8);
404 
    signal VIDROWS_reg          : std_logic_vector(7 downto 0)  := conv_std_logic_vector(vid_lines, 8);
405 
    signal STDOUT_reg           : std_logic_vector(7 downto 0);
406 
    signal VID_CURSOR           : std_logic_vector(15 downto 0);
407 
    signal LCDON_reg            : std_logic;
408 
         signal RNDNUMBER_reg        : std_logic_vector (random_width-1 downto 0);
409 
 
410 
begin
411 
 
412 
    VGA_BLANK_N <= '1';
413 
    VGA_CLK     <= clk25mhz;
414 
    HEX0 <= HEX_DISP0;
415 
    HEX1 <= HEX_DISP1;
416 
    HEX2 <= HEX_DISP2;
417 
    HEX3 <= HEX_DISP3;
418 
    HEX4 <= HEX_DISP4;
419 
    HEX5 <= HEX_DISP5;
420 
    HEX6 <= HEX_DISP6;
421 
    HEX7 <= HEX_DISP7;
422 
 
423 
        --LCDON_reg <= SW(14);
424 
    Rst_n_s       <= not SW(17);
425 
    --STDOUT_reg  <= DO_CPU when (A = x"57CD" and Wr_n = '0' and MReq_n = '0');
426 
    --CURX_reg    <= DO_CPU when (A = x"57CF" and Wr_n = '0' and MReq_n = '0');
427 
    --CURY_reg    <= DO_CPU when (A = x"57CE" and Wr_n = '0' and MReq_n = '0');
428 
    -- Turbo 10Mhz
429 
    Clk_Z80     <= clk357mhz when SW(16) = '0' else clk10mhz;
430 
 
431 
    --  Write into VRAM and System Variables
432 
    vram_addra  <= A - VRAM_value;
433 
    vram_dina   <= DO_CPU;
434 
    vram_wea    <= '0' when (A >= VRAM_value and A < (VRAM_value + (vid_cols * vid_lines)) and Wr_n = '0' and MReq_n = '0') else
435 
                   '1';
436 
 
437 
    -- Write into char ram
438 
    cram_addra  <= A - CHARRAM_value;
439 
    cram_dina   <= DO_CPU;
440 
    cram_wea    <= '0' when (A >= CHARRAM_value and A < RAMBOTT_value and Wr_n = '0' and MReq_n = '0') else '1';
441 
 
442 
    -- Write into LCD video ram
443 
    lcdvram(CONV_INTEGER(A - LCD_value)) <= DO_CPU when A >= LCD_value and (A < LCD_value + 32) and Wr_n = '0' and MReq_n = '0';
444 
 
445 
    lcd_printchar: process(clk400hz)
446 
    begin
447 
        if rising_edge(clk400hz) then
448 
            next_char_sig <= lcdvram(CONV_INTEGER(char_count_sig));
449 
        end if;
450 
   end process;
451 
 
452 
    -- SRAM control signals
453 
    -- SRAM will store data for video, characters patterns and RAM (only on DE1 version)
454 
    -- Due to limitation in dual-port block rams on this platform
455 
 
456 
    SRAM_ADDR(15 downto 0)  <= A - VRAM_value;
457 
    SRAM_DQ(7 downto 0)     <= DO_CPU when (Wr_n = '0' and MREQ_n = '0' and A >= VRAM_value) else
458 
                                    (others => 'Z');
459 
    SRAM_WE_N               <= '0' when (Wr_n = '0' and MREQ_n = '0' and A >= VRAM_value) else '1';
460 
    SRAM_OE_N               <= '0' when (Rd_n = '0' and MREQ_n = '0' and A >= VRAM_value) else '1';
461 
    SRAM_DQ(15 downto 8)    <= (others => 'Z');
462 
    SRAM_ADDR(19 downto 16) <= "0000";
463 
    SRAM_UB_N               <= '1';
464 
    SRAM_LB_N               <= '0';
465 
    SRAM_CE_N               <= '0';
466 
 
467 
    -- Input to Z80
468 
    DI_CPU <= ("00000" & Z80SOC_Arch_reg) when (Rd_n = '0' and MREQ_n = '0' and A = Z80SOC_Arch_addr) else
469 
                  RNDNUMBER_reg(7 downto 0)   when (Rd_n = '0' and MREQ_n = '0' and A = x"57C9") else
470 
                          RNDNUMBER_reg(15 downto 8)  when (Rd_n = '0' and MREQ_n = '0' and A = x"57CA") else
471 
              ps2_ascii_reg               when (Rd_n = '0' and MREQ_n = '0' and A = KEYPRESS_addr) else
472 
                      VIDCOLS_reg                 when (Rd_n = '0' and MREQ_n = '0' and A = x"57CC") else
473 
              VIDROWS_reg                 when (Rd_n = '0' and MREQ_n = '0' and A = x"57CB") else
474 
                          STACK_reg(7 downto 0)       when (Rd_n = '0' and MREQ_n = '0' and A = STACK_addr) else
475 
              STACK_reg(15 downto 8)      when (Rd_n = '0' and MREQ_n = '0' and (A = STACK_addr + 1)) else
476 
              RAMTOP_reg(7 downto 0)      when (Rd_n = '0' and MREQ_n = '0' and A = RAMTOP_addr) else
477 
              RAMTOP_reg(15 downto 8)     when (Rd_n = '0' and MREQ_n = '0' and (A = RAMTOP_addr + 1)) else
478 
              RAMBOTT_reg(7 downto 0)     when (Rd_n = '0' and MREQ_n = '0' and A = RAMBOTT_addr) else
479 
              RAMBOTT_reg(15 downto 8)    when (Rd_n = '0' and MREQ_n = '0' and (A = RAMBOTT_addr + 1)) else
480 
              LCD_reg(7 downto 0)         when (Rd_n = '0' and MREQ_n = '0' and A = LCD_addr) else
481 
              LCD_reg(15 downto 8)        when (Rd_n = '0' and MREQ_n = '0' and (A = LCD_addr + 1)) else
482 
              VRAM_reg(7 downto 0)        when (Rd_n = '0' and MREQ_n = '0' and A = VRAM_addr) else
483 
              VRAM_reg(15 downto 8)       when (Rd_n = '0' and MREQ_n = '0' and (A = VRAM_addr + 1)) else
484 
              CHARRAM_reg(7 downto 0)     when (Rd_n = '0' and MREQ_n = '0' and A = CHARRAM_addr) else
485 
              CHARRAM_reg(15 downto 8)    when (Rd_n = '0' and MREQ_n = '0' and (A = CHARRAM_addr + 1)) else
486 
              D_ROM                       when (Rd_n = '0' and MREQ_n = '0' and IORQ_n = '1' and A < VRAM_value) else
487 
              SRAM_DQ(7 downto 0)         when (Rd_n = '0' and MREQ_n = '0' and IORQ_n = '1' and A >= VRAM_value) else
488 
              SW(7 downto 0)              when (Rd_n = '0' and MREQ_n = '1' and IORQ_n = '0' and A(7 downto 0) = x"20") else
489 
              SW(15 downto 8)             when (Rd_n = '0' and MREQ_n = '1' and IORQ_n = '0' and A(7 downto 0) = x"21") else
490 
              ("0000" & not KEY)          when (Rd_n = '0' and MREQ_n = '1' and IORQ_n = '0' and A(7 downto 0) = x"30") else
491 
              "ZZZZZZZZ";
492 
 
493 
    -- Process to latch leds and hex displays
494 
    pinout_process: process(Clk_Z80)
495 
    variable NUMBER0_sig : std_logic_vector(3 downto 0);
496 
    variable NUMBER1_sig : std_logic_vector(3 downto 0);
497 
    variable NUMBER2_sig : std_logic_vector(3 downto 0);
498 
    variable NUMBER3_sig : std_logic_vector(3 downto 0);
499 
    variable NUMBER4_sig : std_logic_vector(3 downto 0);
500 
    variable NUMBER5_sig : std_logic_vector(3 downto 0);
501 
    variable NUMBER6_sig : std_logic_vector(3 downto 0);
502 
    variable NUMBER7_sig : std_logic_vector(3 downto 0);
503 
    variable LEDG_sig    : std_logic_vector(7 downto 0);
504 
    variable LEDR_sig    : std_logic_vector(15 downto 0);
505 
 
506 
    begin
507 
        if Clk_Z80'event and Clk_Z80 = '1' then
508 
          if IORQ_n = '0' and MREQ_n = '1' and Wr_n = '0' then
509 
            -- LEDG
510 
            if A(7 downto 0) = x"01" then
511 
                LEDG_sig := DO_CPU;
512 
            -- LEDR
513 
            elsif A(7 downto 0) = x"02" then
514 
                LEDR_sig(7 downto 0) := DO_CPU;
515 
            elsif A(7 downto 0) = x"03" then
516 
                LEDR_sig(15 downto 8) := DO_CPU;
517 
            -- HEX1 and HEX0
518 
            elsif A(7 downto 0) = x"10" then
519 
                NUMBER0_sig := DO_CPU(3 downto 0);
520 
                NUMBER1_sig := DO_CPU(7 downto 4);
521 
            -- HEX3 and HEX2
522 
            elsif A(7 downto 0) = x"11" then
523 
                NUMBER2_sig := DO_CPU(3 downto 0);
524 
                NUMBER3_sig := DO_CPU(7 downto 4);
525 
            -- HEX5 and HEX4
526 
            elsif A(7 downto 0) = x"12" then
527 
                NUMBER4_sig := DO_CPU(3 downto 0);
528 
                NUMBER5_sig := DO_CPU(7 downto 4);
529 
            -- HEX7 and HEX6
530 
            elsif A(7 downto 0) = x"13" then
531 
                NUMBER6_sig := DO_CPU(3 downto 0);
532 
                NUMBER7_sig := DO_CPU(7 downto 4);
533 
            elsif A(7 downto 0) = x"15" then
534 
                LCDON_reg <= DO_CPU(0);
535 
            end if;
536 
                    else
537 
                    -- DEBUG ADDRESS BUSS
538 
                            LEDR_sig(15 DOWNTO 0) := A;
539 
          end if;
540 
        end if;
541 
 
542 
        -- Latches the signals
543 
        LEDR(15 downto 0) <= LEDR_sig;
544 
        LEDG(7 downto 0)  <= LEDG_sig;
545 
        NUMBER0           <= NUMBER0_sig;
546 
        NUMBER1           <= NUMBER1_sig;
547 
        NUMBER2           <= NUMBER2_sig;
548 
        NUMBER3           <= NUMBER3_sig;
549 
        NUMBER4           <= NUMBER4_sig;
550 
        NUMBER5           <= NUMBER5_sig;
551 
        NUMBER6           <= NUMBER6_sig;
552 
        NUMBER7           <= NUMBER7_sig;
553 
    end process;
554 
 
555 
    -- the following three processes deals with different clock domain signals
556 
        -- to interface with the PS/2 keyboard
557 
    ps2_process1: process(CLOCK_50)
558 
    begin
559 
        if CLOCK_50'event and CLOCK_50 = '1' then
560 
            if ps2_read = '1' then
561 
                if ps2_ascii_sig /= x"FF" then
562 
                    ps2_read <= '0';
563 
                    ps2_ascii_reg1 <= "00000000";
564 
                end if;
565 
            elsif ps2_scan_ready = '1' then
566 
                if ps2_ascii_sig = x"FF" then
567 
                    ps2_read <= '1';
568 
                else
569 
                    ps2_ascii_reg1 <= ps2_ascii_sig;
570 
                end if;
571 
            end if;
572 
        end if;
573 
    end process;
574 
 
575 
    ps2_process2: process(Clk_Z80)
576 
    begin
577 
        if Clk_Z80'event and Clk_Z80 = '1' then
578 
            ps2_ascii_reg <= ps2_ascii_reg1;
579 
        end if;
580 
    end process;
581 
 
582 
         random: process(CLOCK_50)
583 
        variable rand_temp : std_logic_vector(random_width-1 downto 0):=(random_width-1 => '1',others => '0');
584 
        variable temp : std_logic := '0';
585 
        begin
586 
        if(rising_edge(CLOCK_50)) then
587 
            temp := rand_temp(random_width-1) xor rand_temp(random_width-2);
588 
            rand_temp(random_width-1 downto 1) := rand_temp(random_width-2 downto 0);
589 
            rand_temp(0) := temp;
590 
        end if;
591 
        RNDNUMBER_reg <= rand_temp;
592 
         end process;
593 
 
594 
 
595 
    One <= '1';
596 
    z80_inst: T80se
597 
    port map (
598 
        M1_n                    => open,
599 
        MREQ_n                  => MREQ_n,
600 
        IORQ_n                  => IORQ_n,
601 
        RD_n                    => Rd_n,
602 
        WR_n                    => Wr_n,
603 
        RFSH_n                  => open,
604 
        HALT_n                  => open,
605 
        WAIT_n                  => One,
606 
        INT_n                   => One,
607 
        NMI_n                   => One,
608 
        RESET_n                 => Rst_n_s,
609 
        BUSRQ_n                 => One,
610 
        BUSAK_n                 => open,
611 
        CLK_n                   => Clk_Z80,
612 
        CLKEN                   => One,
613 
        A                       => A,
614 
        DI                      => DI_CPU,
615 
        DO                      => DO_CPU
616 
    );
617 
 
618 
    video_inst: video
619 
        port map (
620 
        CLOCK_25                => clk25mhz,
621 
        VRAM_DATA               => vram_doutb,
622 
        VRAM_ADDR               => vram_addrb(13 downto 0),
623 
        VRAM_CLOCK              => vram_clkb,
624 
        VRAM_WREN               => vram_web,
625 
        CRAM_DATA               => cram_doutb,
626 
        CRAM_ADDR               => cram_addrb(10 downto 0),
627 
        CRAM_WEB                => cram_web,
628 
        VGA_R                   => VGA_R(7 downto 4),
629 
        VGA_G                   => VGA_G(7 downto 4),
630 
        VGA_B                   => VGA_B(7 downto 4),
631 
        VGA_HS                  => VGA_HS,
632 
        VGA_VS                  => VGA_VS
633 
    );
634 
 
635 
    vram_inst : vram
636 
    port map (
637 
        rdclock                 => vram_clkb,
638 
        wrclock                 => Clk_Z80,
639 
        wren                    => not vram_wea, -- inverted logic so code is similar to SRAM and S3E port
640 
        wraddress               => vram_addra(12 downto 0),
641 
        rdaddress               => vram_addrb(12 downto 0),
642 
        data                    => vram_dina,
643 
        q                       => vram_doutb
644 
    );
645 
 
646 
    cram: charram
647 
    port map (
648 
        rdaddress               => cram_addrb(10 downto 0),
649 
        wraddress               => cram_addra(10 downto 0),
650 
        wrclock                 => Clk_Z80,
651 
        rdclock                 => vram_clkb,
652 
        data                    => cram_dina,
653 
        q                       => cram_doutb,
654 
        wren                    => NOT cram_wea
655 
    );
656 
 
657 
    rom_inst: rom
658 
    port map (
659 
        clock                   => clk25mhz,
660 
        address                 => A(13 downto 0),
661 
        q                       => D_ROM
662 
    );
663 
 
664 
    clkdiv_inst: clk_div
665 
    port map (
666 
        clock_in_50mhz          => CLOCK_50,
667 
        clock_25mhz             => clk25mhz,
668 
        clock_10MHz             => clk10mhz,
669 
        clock_357Mhz            => clk357mhz,
670 
        clock_1MHz              => clk1mhz,
671 
        clock_100KHz            => open,
672 
        clock_10KHz             => open,
673 
        clock_1KHz              => clk1khz,
674 
        clock_100Hz             => clk100hz,
675 
        clock_10Hz              => clk10hz,
676 
        clock_1Hz               => clk1hz
677 
    );
678 
 
679 
    DISPHEX0 : decoder_7seg
680 
        port map (
681 
        NUMBER                  =>  NUMBER0,
682 
        HEX_DISP                =>  HEX_DISP0
683 
    );
684 
 
685 
    DISPHEX1 : decoder_7seg
686 
        port map (
687 
        NUMBER                  =>  NUMBER1,
688 
        HEX_DISP                =>  HEX_DISP1
689 
    );
690 
 
691 
    DISPHEX2 : decoder_7seg
692 
        port map (
693 
        NUMBER                  =>  NUMBER2,
694 
        HEX_DISP                =>  HEX_DISP2
695 
    );
696 
 
697 
    DISPHEX3 : decoder_7seg
698 
        port map (
699 
        NUMBER                  =>  NUMBER3,
700 
        HEX_DISP                =>  HEX_DISP3
701 
    );
702 
 
703 
        DISPHEX4 : decoder_7seg
704 
                port map (
705 
        NUMBER                  =>  NUMBER4,
706 
        HEX_DISP                =>  HEX_DISP4
707 
    );
708 
 
709 
    DISPHEX5 : decoder_7seg
710 
        port map (
711 
        NUMBER                  =>  NUMBER5,
712 
        HEX_DISP                =>  HEX_DISP5
713 
    );
714 
 
715 
    DISPHEX6 : decoder_7seg
716 
        port map (
717 
        NUMBER                  =>  NUMBER6,
718 
        HEX_DISP                =>  HEX_DISP6
719 
    );
720 
 
721 
    DISPHEX7 : decoder_7seg
722 
        port map (
723 
        NUMBER                  =>  NUMBER7,
724 
        HEX_DISP                =>  HEX_DISP7
725 
    );
726 
 
727 
    ps2_kbd_inst : ps2kbd
728 
    port map (
729 
        keyboard_clk            => PS2_CLK,
730 
        keyboard_data           => PS2_DAT,
731 
        clock                   => CLOCK_50,
732 
        clkdelay                => clk100hz,
733 
        reset                   => Rst_n_s,
734 
        read                    => ps2_read,
735 
        scan_ready              => ps2_scan_ready,
736 
        ps2_ascii_code          => ps2_ascii_sig
737 
    );
738 
 
739 
    lcd_inst: lcd
740 
         port map (
741 
        reset                   => Rst_n_s,
742 
        CLOCK_50                => CLOCK_50,
743 
        LCD_RS                  => LCD_RS,
744 
        LCD_EN                  => LCD_EN,
745 
        LCD_RW                  => LCD_RW,
746 
        LCD_ON                  => LCD_ON,
747 
        LCD_DATA                => LCD_DATA(7 DOWNTO 0),
748 
        lcd_on_sig              => LCDON_reg,
749 
        next_char               => next_char_sig,
750 
        char_count              => char_count_sig,
751 
        clk400hz                => clk400hz
752 
    );
753 
 
754 
    --
755 
    UART_TXD    <= 'Z';
756 
    DRAM_ADDR   <= (others => '0');
757 
    DRAM_DQM_0  <= '0';
758 
    DRAM_DQM_1  <= '0';
759 
    DRAM_DQM_2  <= '0';
760 
    DRAM_DQM_3  <= '0';
761 
    DRAM_WE_N   <= '1';
762 
    DRAM_CAS_N  <= '1';
763 
    DRAM_RAS_N  <= '1';
764 
    DRAM_CS_N   <= '1';
765 
    DRAM_BA_0   <= '0';
766 
    DRAM_BA_1   <= '0';
767 
    DRAM_CLK    <= '0';
768 
    DRAM_CKE    <= '0';
769 
    FL_ADDR     <= (others => '0');
770 
    FL_WE_N     <= '1';
771 
    FL_RST_N    <= '0';
772 
    FL_OE_N     <= '1';
773 
    FL_CE_N     <= '1';
774 
    AUD_DACDAT  <= '0';
775 
    AUD_XCK     <= '0';
776 
    -- Set all bidirectional ports to tri-state
777 
    DRAM_DQ     <= (others => 'Z');
778 
    FL_DQ       <= (others => 'Z');
779 
 
780 
    AUD_ADCLRCK <= 'Z';
781 
    AUD_DACLRCK <= 'Z';
782 
    AUD_BCLK    <= 'Z';
783 
end;

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