| 1 |
26 |
Revanth |
## *ZAP* : An ARM compatible core with cache and MMU (ARMv4T ISA compatible)
|
| 2 |
|
|
|
| 3 |
|
|
#### Author : Revanth Kamaraj (revanth91kamaraj@gmail.com)
|
| 4 |
|
|
#### License : GPL v2
|
| 5 |
|
|
|
| 6 |
|
|
### Description
|
| 7 |
|
|
|
| 8 |
|
|
ZAP is a pipelined ARM processor core that can execute the ARMv4T instruction
|
| 9 |
|
|
set. It is equipped with ARMv4 compatible split writeback caches and memory
|
| 10 |
|
|
management capabilities. The processor core uses a 10 stage pipeline.
|
| 11 |
|
|
|
| 12 |
|
|
Note that ARM GCC is included in the repository in the *sw* directory. The
|
| 13 |
|
|
makefile will extract the GCC compiler into the object folder.
|
| 14 |
|
|
|
| 15 |
|
|
### Current Status
|
| 16 |
|
|
|
| 17 |
|
|
Experimental.
|
| 18 |
|
|
|
| 19 |
|
|
### Bugs and Known Issues
|
| 20 |
|
|
|
| 21 |
|
|
- Issues with the Thumb ISA.
|
| 22 |
|
|
- SWAP does not bypass cache.
|
| 23 |
|
|
|
| 24 |
|
|
### Bus Interface
|
| 25 |
|
|
|
| 26 |
|
|
Wishbone B3 compatible 32-bit bus.
|
| 27 |
|
|
|
| 28 |
|
|
### Documentation
|
| 29 |
|
|
|
| 30 |
32 |
Revanth |
Please see the PDF file at *doc/ZAP_PROCESSOR_CORE_DATASHEET.pdf*
|
| 31 |
26 |
Revanth |
|
| 32 |
|
|
### Features
|
| 33 |
|
|
|
| 34 |
|
|
- Fully synthesizable Verilog-2001 core.
|
| 35 |
|
|
- Store buffer for improved performance.
|
| 36 |
|
|
- Can execute ARMv4T code. Note that compressed instruction support is EXPERIMENTAL.
|
| 37 |
|
|
- Wishbone B3 compatible interface. Cache unit supports burst access.
|
| 38 |
|
|
- 10-stage pipeline design. Pipeline has bypass network to resolve dependencies.
|
| 39 |
|
|
- 2 write ports for the register file to allow LDR/STR with writeback to execute as a single instruction.
|
| 40 |
|
|
- Branch prediction supported.
|
| 41 |
|
|
- Split I and D writeback cache (Size can be configured using parameters).
|
| 42 |
|
|
- Split I and D MMUs (TLB size can be configured using parameters).
|
| 43 |
|
|
- Base restored abort model to simplify data abort handling.
|
| 44 |
|
|
|
| 45 |
42 |
Revanth |
### License
|
| 46 |
|
|
|
| 47 |
|
|
(C) 2016-2018 Revanth Kamaraj.
|
| 48 |
|
|
|
| 49 |
|
|
This program is free software; you can redistribute it and/or
|
| 50 |
|
|
modify it under the terms of the GNU General Public License
|
| 51 |
|
|
as published by the Free Software Foundation; either version 2
|
| 52 |
|
|
of the License, or (at your option) any later version.
|
| 53 |
|
|
|
| 54 |
|
|
This program is distributed in the hope that it will be useful,
|
| 55 |
|
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| 56 |
|
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
| 57 |
|
|
GNU General Public License for more details.
|
| 58 |
|
|
|
| 59 |
|
|
You should have received a copy of the GNU General Public License
|
| 60 |
|
|
along with this program; if not, write to the Free Software
|
| 61 |
|
|
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
|
| 62 |
|
|
02110-1301, USA.
|
| 63 |
|
|
|
| 64 |
|
|
|
