1 |
2 |
zeus |
`timescale 1ns/10ps
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2 |
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3 |
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module alu(x, y, out, t, func, iflags, oflags, word_op, seg, off);
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4 |
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// IO ports
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input [/* 31 */ 15:0] x;
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input [15:0] y;
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7 |
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input [2:0] t, func;
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8 |
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input [15:0] iflags;
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9 |
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input word_op;
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10 |
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input [15:0] seg, off;
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output [31:0] out;
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output [8:0] oflags;
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13 |
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// Net declarations
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15 |
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wire [15:0] add /* adj, log, shi, rot */;
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16 |
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wire [8:0] othflags;
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17 |
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wire [19:0] oth;
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18 |
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// wire [31:0] cnv, mul;
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19 |
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// wire af_add, af_adj;
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// wire cf_adj, cf_add, cf_mul, cf_log, cf_shi, cf_rot;
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21 |
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// wire of_adj, of_add, of_mul, of_log, of_shi, of_rot;
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22 |
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wire /* ofi, */ sfi, zfi, /* afi, */ pfi, cfi;
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wire /* ofo, */ sfo, zfo, /* afo, */ pfo /*, cfo */;
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wire flags_unchanged;
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25 |
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// Module instances
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addsub ad0(x[15:0], y, add, func, word_op, cfi, /* cf_add */, /* af_add, */
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28 |
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/* of_add */);
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29 |
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/*
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30 |
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adj adj0(x[15:0], y, {cf_adj, adj}, func, afi, cfi, af_adj, of_adj);
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31 |
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conv cnv0(x[15:0], cnv, func[0]);
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32 |
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muldiv mul0(x, y, mul, func[1:0], word_op, cf_mul, of_mul);
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33 |
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bitlog lo0(x[15:0], y, log, func, cf_log, of_log);
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34 |
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shifts sh0(x[15:0], y, shi, func[1:0], word_op, cfi, ofi, cf_shi, of_shi);
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35 |
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rotat rot0(x[15:0], y, rot, func[1:0], word_op, cfi, cf_rot, of_rot);
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36 |
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*/
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othop oth0(x[15:0], y, seg, off, iflags, func, word_op, oth, othflags);
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mux8_16 m0(t, 16'd0/* adj */, add, 16'd0/* cnv[15:0] */,
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16'd0 /* mul[15:0] */, 16'd0 /* log */, 16'd0 /* shi */,
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16'd0 /* rot */, oth[15:0], out[15:0]);
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42 |
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mux8_16 m1(t, 16'd0, 16'd0, 16'd0 /* cnv[31:16] */, 16'd0 /* mul[31:16] */,
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16'd0, 16'd0, 16'd0, {12'b0,oth[19:16]}, out[31:16]);
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// mux8_1 a1(t, cf_adj, cf_add, cfi, cf_mul, cf_log, cf_shi, cf_rot, 1'b0, cfo);
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// mux8_1 a2(t, af_adj, af_add, afi, 1'b0, 1'b0, 1'b0, afi, 1'b0, afo);
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// mux8_1 a3(t, of_adj, of_add, ofi, of_mul, of_log, of_shi, of_rot, 1'b0, ofo);
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47 |
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48 |
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// Flags
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assign pfo = flags_unchanged ? pfi : ^~ out[7:0];
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assign zfo = flags_unchanged ? zfi : (word_op ? ~|out[15:0] : ~|out[7:0]);
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assign sfo = flags_unchanged ? sfi : (word_op ? out[15] : out[7]);
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assign oflags = (t == 3'd7) ? othflags
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: { 1'b0 /* ofo */, iflags[10:8], sfo, zfo, 1'b0 /* afo */,
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pfo, 1'b0 /* cfo */ };
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// assign ofi = iflags[11];
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assign sfi = iflags[7];
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assign zfi = iflags[6];
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60 |
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// assign afi = iflags[4];
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assign pfi = iflags[2];
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assign cfi = iflags[0];
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assign flags_unchanged = (t == 4'd6 || t == 4'd2 || t == 4'd4 && func == 4'd1);
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endmodule
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module addsub(x, y, out, func, word_op, cfi, cfo, /* afo, */ ofo);
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// IO ports
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input [15:0] x, y;
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input [2:0] func;
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input cfi, word_op;
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output cfo, /* afo, */ ofo;
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output [15:0] out;
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// Net declarations
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76 |
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wire [16:0] adc, add, ad8, dec, neg, sbb, sub, cmp;
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77 |
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// wire [4:0] tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7;
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78 |
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wire resta, bneg, bincdec, cfo8, cfo16, ofo8, ofo16, cfoneg8, cfoneg16;
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// wire afo_adc, afo_add, afo_inc, afo_dec, afo_neg, afo_sbb, afo_sub, afo_cmp;
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wire [16:0] out17;
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81 |
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// Module instances
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mux8_17 m0(func, adc, add, ad8, dec, neg, sbb, sub, cmp, out17);
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/* mux8_1 m1(func, afo_adc, afo_add, afo_inc, afo_dec,
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afo_neg, afo_sbb, afo_sub, afo_cmp, afo); */
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// Assignments
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assign adc = x + y + cfi;
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assign add = x + y;
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assign ad8 = x + y[7:0];
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91 |
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assign dec = x - 8'b1;
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assign neg = {x==16'd0 ? 1'b0 : 1'b1, -x};
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assign sbb = x - y - cfi;
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assign sub = x - y;
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assign cmp = x - y;
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/*
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assign tmp0 = x[3:0] + y[3:0] + cfi;
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98 |
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assign tmp1 = x[3:0] + y[3:0];
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99 |
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assign tmp2 = x[3:0] + 4'b1;
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100 |
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assign tmp3 = x[3:0] - 4'b1;
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101 |
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assign tmp4 = -x[3:0];
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102 |
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assign tmp5 = x[3:0] - y[3:0] -cfi;
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assign tmp6 = x[3:0] - y[3:0];
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104 |
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assign tmp7 = x[3:0] - y[3:0];
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105 |
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106 |
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assign afo_adc = tmp0[4];
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107 |
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assign afo_add = tmp1[4];
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108 |
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assign afo_inc = tmp2[4];
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109 |
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assign afo_dec = tmp3[4];
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110 |
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assign afo_neg = tmp4[4];
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111 |
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assign afo_sbb = tmp5[4];
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112 |
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assign afo_sub = tmp6[4];
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113 |
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assign afo_cmp = tmp7[4];
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114 |
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*/
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115 |
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assign resta = (func > 3'd2);
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116 |
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assign bneg = (func == 3'd4);
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117 |
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assign ofo16 = resta ? ( bneg ? x[15] & out[15] :
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118 |
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(~x[15] & y[15] & out[15] | x[15] & ~y[15] & ~out[15]))
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119 |
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: (~x[15] & ~y[15] & out[15] | x[15] & y[15] & ~out[15]);
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120 |
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121 |
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assign ofo8 = resta ? ( bneg ? x[7] & out[7] :
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122 |
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(~x[7] & y[7] & out[7] | x[7] & ~y[7] & ~out[7]))
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123 |
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: (~x[7] & ~y[7] & out[7] | x[7] & y[7] & ~out[7]);
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124 |
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125 |
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assign cfoneg8 = x[7:0]!=8'd0;
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126 |
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assign cfoneg16 = x[15:0]!=16'd0;
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127 |
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assign bincdec = (func == 3'd2 || func == 3'd3);
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128 |
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assign cfo8 = bneg ? cfoneg8 : out17[8];
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129 |
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assign cfo16 = bneg ? cfoneg16 : out17[16];
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130 |
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assign out = out17[15:0];
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131 |
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assign cfo = bincdec ? cfi : (word_op ? cfo16 : cfo8);
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132 |
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assign ofo = word_op ? ofo16 : ofo8;
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endmodule
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/*
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136 |
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module adj(x, y, out, func, afi, cfi, afo, cfo);
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137 |
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// IO ports
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138 |
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input [15:0] x, y;
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139 |
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input [2:0] func;
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140 |
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input afi, cfi;
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141 |
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output afo, cfo;
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output [16:0] out;
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143 |
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144 |
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// Net declarations
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145 |
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wire [16:0] aaa, aad, aam, aas, daa, das, aad16;
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wire [7:0] ala, als, alout;
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wire alcnd;
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148 |
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// Module instances
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150 |
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mux8_17 m0(func, aaa, aad, aam, aas,
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daa, das, {9'd0, y[7:0]}, {1'b0, y}, out);
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152 |
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153 |
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// Assignments
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154 |
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assign aaa = afo ? { x[15:8] + 8'd1, (x[7:0] + 8'd6) & 8'h0f } : x;
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assign aad16 = x[15:8] * 8'd10 + x[7:0];
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156 |
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assign aad = { 8'b0, aad16[7:0] };
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assign aam = 16'd0; // FIXME: { x[7:0] / 8'd10, x[7:0] % 8'd10 };
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158 |
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assign aas = afo ? { x[15:8] - 8'd1, (x[7:0] - 8'd6) & 8'h0f } : x;
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160 |
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assign ala = afo ? x[7:0] + 8'd6 : x[7:0];
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assign als = afo ? x[7:0] - 8'd6 : x[7:0];
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162 |
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assign alout = (func == 3'd4) ? ala : als;
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assign alcnd = (alout > 8'h9f) | cfi;
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164 |
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assign daa = alcnd ? { x[15:8], x[3:0] + 8'h60 } : { x[15:8], alout };
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assign das = alcnd ? { x[15:8], x[3:0] - 8'h60 } : { x[15:8], alout };
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assign afo = (x[3:0] > 4'd9) | afi;
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assign cfo = func[2] ? alcnd : afo;
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endmodule
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module conv(x, out, func);
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// IO ports
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173 |
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input [15:0] x;
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174 |
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input func; // type = 010 and func = 111 is reserved for INTO
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output [31:0] out;
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// Net declarations
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178 |
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wire [31:0] cbw, cwd;
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wire [23:0] x7_24;
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wire [15:0] x15_16;
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// Assignments
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183 |
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assign x7_24 = { 24{x[7]} };
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184 |
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assign x15_16 = { 16{x[15]} };
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185 |
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assign cbw = { x7_24, x[7:0] };
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186 |
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assign cwd = { x15_16, x[7:0] };
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187 |
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assign out = func ? cwd : cbw;
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endmodule
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190 |
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module muldiv(x, y, out, func, word_op, cfo, ofo);
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// IO ports
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input [31:0] x;
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input [15:0] y;
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input [1:0] func;
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input word_op;
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196 |
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output [31:0] out;
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197 |
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output cfo, ofo;
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198 |
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199 |
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// Net declarations
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200 |
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wire signed [31:0] x_s, imul, idiv32, mods32;
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201 |
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wire signed [15:0] y_s, idivr16, modsr16, idiv16, mods16;
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202 |
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wire signed [7:0] idivr8, modsr8;
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203 |
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wire [31:0] mul, div32, modu32, div, idiv;
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204 |
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wire [15:0] divr16, modur16, div16, modu16;
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205 |
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wire [7:0] divr8, modur8;
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206 |
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wire cfo8, cfo16;
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207 |
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208 |
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// Module instantiations
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209 |
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mux4_32 m0(func, mul, imul, div, idiv, out);
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210 |
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211 |
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// Assignments
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212 |
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assign x_s = x;
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213 |
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assign y_s = y;
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214 |
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assign mul = x[15:0] * y;
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215 |
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assign imul = x_s[15:0] * y_s;
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216 |
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217 |
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assign div32 = x / y;
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218 |
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assign modu32 = x % y;
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219 |
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assign idiv32 = x_s / y_s;
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220 |
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assign mods32 = x_s % y_s;
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221 |
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assign divr16 = div32[15:0];
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222 |
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assign modur16 = modu32[15:0];
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223 |
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assign idivr16 = idiv32[15:0];
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224 |
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assign modsr16 = mods32[15:0];
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225 |
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226 |
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assign div16 = x[15:0] / y[7:0];
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227 |
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assign modu16 = x[15:0] % y[7:0];
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228 |
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assign idiv16 = x_s[15:0] / y_s[7:0];
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229 |
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assign mods16 = x_s[15:0] % y_s[7:0];
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230 |
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assign divr8 = div16[7:0];
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231 |
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assign modur8 = modu16[7:0];
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232 |
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assign idivr8 = idiv16[7:0];
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233 |
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assign modsr8 = mods16[7:0];
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234 |
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235 |
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assign div = word_op ? { modur16, divr16 } : { 16'd0, modur8, divr8 };
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236 |
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assign idiv = word_op ? { modsr16, idivr16 } : { 16'd0, modsr8, idivr8 };
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237 |
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238 |
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assign cfo16 = (out[31:16] != { 16{out[15]} });
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239 |
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assign cfo8 = (out[15:8] != { 8{out[7]} });
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240 |
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assign cfo = word_op ? cfo16 : cfo8;
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241 |
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assign ofo = cfo;
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242 |
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endmodule
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243 |
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244 |
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module bitlog(x, y, out, func, cfo, ofo);
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245 |
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// IO ports
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246 |
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input [15:0] x, y;
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247 |
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input [2:0] func;
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248 |
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output [15:0] out;
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249 |
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output cfo, ofo;
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250 |
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251 |
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// Net declarations
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252 |
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wire [15:0] and_n, or_n, not_n, xor_n, test_n;
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253 |
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254 |
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// Module instantiations
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255 |
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mux8_16 m0(func, and_n, or_n, not_n, xor_n, test_n, 16'd0, 16'd0, 16'd0, out);
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256 |
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257 |
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// Assignments
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258 |
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assign and_n = x & y;
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259 |
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assign or_n = x | y;
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260 |
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assign not_n = ~x;
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261 |
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assign xor_n = x ^ y;
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262 |
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assign test_n = x & y;
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263 |
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264 |
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assign cfo = 1'b0;
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265 |
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assign ofo = 1'b0;
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266 |
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endmodule
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267 |
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268 |
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module shifts(x, y, out, func, word_op, cfi, ofi, cfo, ofo);
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269 |
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// IO ports
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270 |
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input [15:0] x, y;
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271 |
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input [1:0] func;
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272 |
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input cfi, ofi;
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273 |
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input word_op;
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274 |
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output [15:0] out;
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275 |
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output cfo, ofo;
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276 |
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277 |
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// Net declarations
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278 |
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wire [15:0] sal_shl, sar, shr, sar16, shr16;
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279 |
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wire [7:0] sar8, shr8;
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280 |
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wire signed [15:0] x_s;
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281 |
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wire ofo_shl, ofo_sar, ofo_shr, ofo_o, cfo16, cfo8;
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282 |
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283 |
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// Module instantiations
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284 |
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mux4_16 m0(func, sal_shl, sar, shr, 16'd0, out);
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285 |
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mux4_1 m1(func, ofo_shl, ofo_sar, ofo_shr, 1'b0, ofo_o);
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286 |
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287 |
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// Assignments
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288 |
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assign x_s = x;
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289 |
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assign sal_shl = x << y[7:0];
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290 |
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assign sar16 = x_s >>> y[7:0];
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291 |
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assign shr16 = x >> y[7:0];
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292 |
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assign sar8 = x_s[7:0] >>> y[7:0];
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293 |
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assign shr8 = x[7:0] >> y[7:0];
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294 |
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assign shr = word_op ? shr16 : {8'd0, shr8};
|
295 |
|
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assign sar = word_op ? sar16 : {8'd0, sar8};
|
296 |
|
|
|
297 |
|
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assign cfo16 = (y == 16'd0) ? cfi :
|
298 |
|
|
( (func==2'd0) ? |(x & (16'h8000 >> (y-1))) : |(x & (16'h1 << (y-1))));
|
299 |
|
|
assign cfo8 = (y[7:0] == 8'd0) ? cfi :
|
300 |
|
|
( (func==2'd0) ? |(x[7:0] & (8'h80 >> (y-1)))
|
301 |
|
|
: |(x[7:0] & (8'h1 << (y-1))));
|
302 |
|
|
assign cfo = word_op ? cfo16 : cfo8;
|
303 |
|
|
assign ofo = (y == 16'd0) ? ofi : ofo_o;
|
304 |
|
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assign ofo_shl = word_op ? (out[15] != cfo) : (out[7] != cfo);
|
305 |
|
|
assign ofo_sar = 1'b0;
|
306 |
|
|
assign ofo_shr = word_op ? x[15] : x[7];
|
307 |
|
|
endmodule
|
308 |
|
|
|
309 |
|
|
module rotat(x, y, out, func, word_op, cfi, cfo, ofo);
|
310 |
|
|
// IO ports
|
311 |
|
|
input [15:0] x, y;
|
312 |
|
|
input [1:0] func;
|
313 |
|
|
input cfi, word_op;
|
314 |
|
|
output [15:0] out;
|
315 |
|
|
output cfo;
|
316 |
|
|
output ofo;
|
317 |
|
|
|
318 |
|
|
// Net declarations
|
319 |
|
|
wire [15:0] rcl16, rcr16, rol16, ror16, rcl, rcr, rol, ror;
|
320 |
|
|
wire [7:0] yce16, ye16, yce8, ye8, rcl8, rcr8, rol8, ror8, yc16, yc8;
|
321 |
|
|
wire cfo_rcl, cfo_rcr, cfo_rol, cfo_ror;
|
322 |
|
|
|
323 |
|
|
// Module instantiations
|
324 |
|
|
mux4_16 m0(func, rcl, rcr, rol, ror, out);
|
325 |
|
|
mux4_1 m1(func, cfo_rcl, cfo_rcr, cfo_rol, cfo_ror, cfo);
|
326 |
|
|
|
327 |
|
|
// Assignments
|
328 |
|
|
assign yce16 = ye16; // FIXME: y[7:0] % 8'd17;
|
329 |
|
|
assign ye16 = y[7:0] % 8'd16;
|
330 |
|
|
assign rcl16 = yce16 ? (x << yce16 | cfi << (yce16-8'd1) | x >> (8'd17-yce16)) : x;
|
331 |
|
|
assign rcr16 = yce16 ? (x >> yce16 | cfi << (8'd16-yce16) | x << (8'd17-yce16)) : x;
|
332 |
|
|
assign rol16 = (x << ye16 | x >> (8'd16-ye16));
|
333 |
|
|
assign ror16 = (x >> ye16 | x << (8'd16-ye16));
|
334 |
|
|
|
335 |
|
|
assign yce8 = ye8; // FIXME: y[7:0] % 8'd9;
|
336 |
|
|
assign ye8 = y[7:0] % 8'd8;
|
337 |
|
|
assign rcl8 = yce8 ? (x[7:0] << yce8 | cfi << (yce8-8'd1) | x[7:0] >> (8'd9-yce8)) : x[7:0];
|
338 |
|
|
assign rcr8 = yce8 ? (x[7:0] >> yce8 | cfi << (8'd8-yce8) | x[7:0] << (9'd9-yce8)) : x[7:0];
|
339 |
|
|
assign rol8 = (x[7:0] << ye8 | x[7:0] >> (8'd8-ye8));
|
340 |
|
|
assign ror8 = (x[7:0] >> ye8 | x[7:0] << (8'd8-ye8));
|
341 |
|
|
|
342 |
|
|
assign rcl = word_op ? rcl16 : { 8'd0, rcl8 };
|
343 |
|
|
assign rcr = word_op ? rcr16 : { 8'd0, rcr8 };
|
344 |
|
|
assign rol = word_op ? rol16 : { 8'd0, rol8 };
|
345 |
|
|
assign ror = word_op ? ror16 : { 8'd0, ror8 };
|
346 |
|
|
|
347 |
|
|
// Carry
|
348 |
|
|
assign yc16 = (y[7:0]-8'd1)%8'd16;
|
349 |
|
|
assign yc8 = (y[7:0]-8'd1)%8'd8;
|
350 |
|
|
assign cfo_rcl = word_op ? (yce16==8'd0 ? cfi : x[16-yce16])
|
351 |
|
|
: (yce8==8'd0 ? cfi : x[8-yce8]);
|
352 |
|
|
assign cfo_rcr = word_op ? (yce16==8'd0 ? cfi : x[yce16-1])
|
353 |
|
|
: (yce8==8'd0 ? cfi : x[yce8-1]);
|
354 |
|
|
assign cfo_rol = word_op ? (y[7:0]==8'd0 ? cfi : x[15-yc16])
|
355 |
|
|
: (y[7:0]==8'd0 ? cfi : x[7-yc8]);
|
356 |
|
|
assign cfo_ror = word_op ? (y[7:0]==8'd0 ? cfi : x[yc16])
|
357 |
|
|
: (y[7:0]==8'd0 ? cfi : x[yc8]);
|
358 |
|
|
|
359 |
|
|
// Overflow
|
360 |
|
|
assign ofo = func[0] ? // right
|
361 |
|
|
(word_op ? out[15]^out[14] : out[7]^out[6])
|
362 |
|
|
: // left
|
363 |
|
|
(word_op ? cfo^out[15] : cfo^out[7]);
|
364 |
|
|
endmodule
|
365 |
|
|
*/
|
366 |
|
|
|
367 |
|
|
module othop (x, y, seg, off, iflags, func, word_op, out, oflags);
|
368 |
|
|
// IO ports
|
369 |
|
|
input [15:0] x, y, off, seg, iflags;
|
370 |
|
|
input [2:0] func;
|
371 |
|
|
input word_op;
|
372 |
|
|
output [19:0] out;
|
373 |
|
|
output [8:0] oflags;
|
374 |
|
|
|
375 |
|
|
// Net declarations
|
376 |
|
|
wire [15:0] deff, deff2, outf, clcm, setf, intf, strf;
|
377 |
|
|
wire [19:0] dcmp, dcmp2;
|
378 |
|
|
wire dfi;
|
379 |
|
|
|
380 |
|
|
// Module instantiations
|
381 |
|
|
mux8_16 m0(func, dcmp[15:0], dcmp2[15:0], deff, outf, clcm, setf,
|
382 |
|
|
intf, strf, out[15:0]);
|
383 |
|
|
assign out[19:16] = func ? dcmp2[19:16] : dcmp[19:16];
|
384 |
|
|
|
385 |
|
|
// Assignments
|
386 |
|
|
assign dcmp = (seg << 4) + deff;
|
387 |
|
|
assign dcmp2 = (seg << 4) + deff2;
|
388 |
|
|
assign deff = x + y + off;
|
389 |
|
|
assign deff2 = x + y + off + 16'd2;
|
390 |
|
|
assign outf = y;
|
391 |
|
|
assign clcm = y[2] ? (y[1] ? /* -1: clc */ {iflags[15:1], 1'b0}
|
392 |
|
|
: /* 4: cld */ {iflags[15:11], 1'b0, iflags[9:0]})
|
393 |
|
|
: (y[1] ? /* 2: cli */ {iflags[15:10], 1'b0, iflags[8:0]}
|
394 |
|
|
: /* 0: cmc */ {iflags[15:1], ~iflags[0]});
|
395 |
|
|
assign setf = y[2] ? (y[1] ? /* -1: stc */ {iflags[15:1], 1'b1}
|
396 |
|
|
: /* 4: std */ {iflags[15:11], 1'b1, iflags[9:0]})
|
397 |
|
|
: (y[1] ? /* 2: sti */ {iflags[15:10], 1'b1, iflags[8:0]}
|
398 |
|
|
: /* 0: outf */ iflags);
|
399 |
|
|
|
400 |
|
|
assign intf = {iflags[15:10], 2'b0, iflags[7:0]};
|
401 |
|
|
assign dfi = iflags[10];
|
402 |
|
|
assign strf = dfi ? (x - y) : (x + y);
|
403 |
|
|
|
404 |
|
|
assign oflags = word_op ? { out[11:6], out[4], out[2], out[0] }
|
405 |
|
|
: { iflags[11:8], out[7:6], out[4], out[2], out[0] };
|
406 |
|
|
endmodule
|