OpenCores
URL https://opencores.org/ocsvn/zet86/zet86/trunk

Subversion Repositories zet86

[/] [zet86/] [tags/] [INITIAL/] [uart16550/] [altera/] [uart_test.v] - Blame information for rev 49

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 zeus 
`include "../verilog/uart_defines.v"
2 
 
3 
module uart_test(clk_, stxo_, led_);
4 
  // Module IO ports
5 
  input clk_;
6 
  output stxo_;
7 
  output reg [7:0] led_;
8 
 
9 
  // Net declarations
10 
  wire clk, boot;
11 
  reg   [4:0]   wb_adr_i;
12 
  reg   [31:0]  wb_dat_i;
13 
  wire  [31:0]  wb_dat_o;
14 
  reg   [3:0]   wb_sel_i;
15 
  wire  wb_ack_o;
16 
  reg   wb_rst_i, wb_we_i, wb_stb_i, wb_cyc_i;
17 
 
18 
  // Module instantiations
19 
  uart_top uart_snd(clk,
20 
    wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i,
21 
    wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i, /* int_o */,
22 
    stxo_,,
23 
    /* rts_o */, 1'b1, /* dtr_o */, 1'b1, 1'b1, 1'b1);
24 
  altpll0 pll0(clk_, clk, boot);
25 
 
26 
  always @(posedge clk)
27 
    if (~boot)
28 
      begin
29 
        led_     <= 8'd1;
30 
        wb_rst_i <= 1'b1;
31 
        wb_adr_i <= 5'bxxxxx;
32 
        wb_dat_i <= 32'hxxxx_xxxx;
33 
        wb_cyc_i <= 1'b0;
34 
        wb_stb_i <= 1'b0;
35 
        wb_sel_i <= 4'hx;
36 
        wb_we_i  <= 1'hx;
37 
      end
38 
    else
39 
      case (led_)
40 
        8'd01: begin wb_rst_i <= 1'b0; led_ <= 8'd02; end
41 
 
42 
        // wbm.wb_wr1(`UART_REG_LC, 4'b1000, {8'b10011011, 24'b0});
43 
        8'd02: begin
44 
                 wb_adr_i <= `UART_REG_LC;
45 
                 wb_dat_i <= {8'b10011011, 24'b0};
46 
                 wb_cyc_i <= 1'b1;
47 
                 wb_stb_i <= 1'b1;
48 
                 wb_we_i  <= 1'b1;
49 
                 wb_sel_i <= 4'b1000;
50 
                 led_ <= 8'd03;
51 
               end
52 
        8'd03: if (wb_ack_o)
53 
                 begin
54 
                   wb_cyc_i <= 1'b0;
55 
                   wb_stb_i <= 1'b0;
56 
                   wb_adr_i <= 5'bxxxxx;
57 
                   wb_dat_i <= 32'hxxxx_xxxx;
58 
                   wb_we_i  <= 1'hx;
59 
                   wb_sel_i <= 4'hx;
60 
                   led_ <= 8'd04;
61 
                 end
62 
 
63 
        // set dl to divide by 3
64 
        // wbm.wb_wr1(`UART_REG_DL1,4'b0001, 32'd2);
65 
        8'd04: begin
66 
                 wb_adr_i <= `UART_REG_DL1;
67 
                 wb_dat_i <= 32'd3;
68 
                 wb_cyc_i <= 1'b1;
69 
                 wb_stb_i <= 1'b1;
70 
                 wb_we_i  <= 1'b1;
71 
                 wb_sel_i <= 4'b0001;
72 
                 led_ <= 8'd05;
73 
               end
74 
        8'd05: if (wb_ack_o)
75 
                 begin
76 
                   wb_cyc_i <= 1'b0;
77 
                   wb_stb_i <= 1'b0;
78 
                   wb_adr_i <= 5'bxxxxx;
79 
                   wb_dat_i <= 32'hxxxx_xxxx;
80 
                   wb_we_i  <= 1'hx;
81 
                   wb_sel_i <= 4'hx;
82 
                   led_     <= 8'd06;
83 
                 end
84 
 
85 
        // restore normal registers
86 
        // wbm.wb_wr1(`UART_REG_LC, 4'b1000, {8'b00011011, 24'b0});
87 
        8'd06: begin
88 
                 wb_adr_i <= `UART_REG_LC;
89 
                 wb_dat_i <= {8'b00011011, 24'b0};
90 
                 wb_cyc_i <= 1'b1;
91 
                 wb_stb_i <= 1'b1;
92 
                 wb_we_i  <= 1'b1;
93 
                 wb_sel_i <= 4'b1000;
94 
                 led_     <= 8'd07;
95 
               end
96 
        8'd07: if (wb_ack_o)
97 
                 begin
98 
                   wb_cyc_i <= 1'b0;
99 
                   wb_stb_i <= 1'b0;
100 
                   wb_adr_i <= 5'bxxxxx;
101 
                   wb_dat_i <= 32'hxxxx_xxxx;
102 
                   wb_we_i  <= 1'hx;
103 
                   wb_sel_i <= 4'hx;
104 
                   led_     <= 8'd08;
105 
               end
106 
 
107 
        // wb_wr1(5'd0, 4'b1, 32'b10000001);
108 
        8'd08: begin
109 
                 wb_adr_i <= 5'd0;
110 
                 wb_dat_i <= 32'h5a;
111 
                 wb_cyc_i <= 1'b1;
112 
                 wb_stb_i <= 1'b1;
113 
                 wb_we_i  <= 1'b1;
114 
                 wb_sel_i <= 4'b1;
115 
                 led_     <= 8'd09;
116 
               end
117 
        8'd09: if (wb_ack_o)
118 
                 begin
119 
                   wb_cyc_i <= 1'b0;
120 
                   wb_stb_i <= 1'b0;
121 
                   wb_adr_i <= 5'bxxxxx;
122 
                   wb_dat_i <= 32'hxxxx_xxxx;
123 
                   wb_we_i  <= 1'hx;
124 
                   wb_sel_i <= 4'hx;
125 
                   led_     <= 8'd10;
126 
                 end
127 
 
128 
        // wb_wr1(5'd0, 4'b1, 32'b01000010);
129 
        8'd10: begin
130 
                 wb_adr_i <= 5'd0;
131 
                 wb_dat_i <= 32'h65;
132 
                 wb_cyc_i <= 1'b1;
133 
                 wb_stb_i <= 1'b1;
134 
                 wb_we_i  <= 1'b1;
135 
                 wb_sel_i <= 4'b1;
136 
                 led_     <= 8'd11;
137 
               end
138 
        8'd11: if (wb_ack_o)
139 
                 begin
140 
                   wb_cyc_i <= 1'b0;
141 
                   wb_stb_i <= 1'b0;
142 
                   wb_adr_i <= 5'bxxxxx;
143 
                   wb_dat_i <= 32'hxxxx_xxxx;
144 
                   wb_we_i  <= 1'hx;
145 
                   wb_sel_i <= 4'hx;
146 
                   led_     <= 8'd12;
147 
                 end
148 
 
149 
        8'd12: begin
150 
                 wb_adr_i <= 5'd0;
151 
                 wb_dat_i <= 32'h75;
152 
                 wb_cyc_i <= 1'b1;
153 
                 wb_stb_i <= 1'b1;
154 
                 wb_we_i  <= 1'b1;
155 
                 wb_sel_i <= 4'b1;
156 
                 led_     <= 8'd13;
157 
               end
158 
        8'd13: if (wb_ack_o)
159 
                 begin
160 
                   wb_cyc_i <= 1'b0;
161 
                   wb_stb_i <= 1'b0;
162 
                   wb_adr_i <= 5'bxxxxx;
163 
                   wb_dat_i <= 32'hxxxx_xxxx;
164 
                   wb_we_i  <= 1'hx;
165 
                   wb_sel_i <= 4'hx;
166 
                   led_     <= 8'd14;
167 
                 end
168 
        8'd14: begin
169 
                 wb_adr_i <= 5'd0;
170 
                 wb_dat_i <= 32'h73;
171 
                 wb_cyc_i <= 1'b1;
172 
                 wb_stb_i <= 1'b1;
173 
                 wb_we_i  <= 1'b1;
174 
                 wb_sel_i <= 4'b1;
175 
                 led_     <= 8'd15;
176 
               end
177 
        8'd15: if (wb_ack_o)
178 
                 begin
179 
                   wb_cyc_i <= 1'b0;
180 
                   wb_stb_i <= 1'b0;
181 
                   wb_adr_i <= 5'bxxxxx;
182 
                   wb_dat_i <= 32'hxxxx_xxxx;
183 
                   wb_we_i  <= 1'hx;
184 
                   wb_sel_i <= 4'hx;
185 
                   led_     <= 8'd16;
186 
                 end
187 
      endcase
188 
 
189 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.