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# Copyright (C) 1991-2007 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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# The default values for assignments are stored in the file
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# uart_top_assignment_defaults.qdf
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# If this file doesn't exist, and for assignments not listed, see file
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# assignment_defaults.qdf
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# Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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# Copyright (C) 1991-2007 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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# The default values for assignments are stored in the file
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# uart_top_assignment_defaults.qdf
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# If this file doesn't exist, and for assignments not listed, see file
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# assignment_defaults.qdf
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# Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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set_global_assignment -name DEVICE EP2S60F672C5ES
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set_global_assignment -name FAMILY "Stratix II"
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set_global_assignment -name TOP_LEVEL_ENTITY uart_test
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.1 SP1"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:20:04 AUGUST 27, 2007"
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set_global_assignment -name LAST_QUARTUS_VERSION "7.1 SP1"
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
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set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation
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set_global_assignment -name VERILOG_FILE altpll0.v
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set_global_assignment -name VERILOG_FILE uart_test.v
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set_global_assignment -name VERILOG_FILE ../verilog/uart_wb.v
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set_global_assignment -name VERILOG_FILE ../verilog/timescale.v
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set_global_assignment -name VERILOG_FILE ../verilog/uart_debug_if.v
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set_global_assignment -name VERILOG_FILE ../verilog/uart_defines.v
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set_global_assignment -name VERILOG_FILE ../verilog/uart_receiver.v
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set_global_assignment -name VERILOG_FILE ../verilog/uart_regs.v
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set_global_assignment -name VERILOG_FILE ../verilog/uart_rfifo.v
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set_global_assignment -name VERILOG_FILE ../verilog/uart_sync_flops.v
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set_global_assignment -name VERILOG_FILE ../verilog/uart_tfifo.v
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set_global_assignment -name VERILOG_FILE ../verilog/uart_top.v
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set_global_assignment -name VERILOG_FILE ../verilog/uart_transmitter.v
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set_global_assignment -name VERILOG_FILE ../verilog/raminfr.v
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
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set_location_assignment PIN_K8 -to stxo_
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set_location_assignment PIN_AF15 -to clk_
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set_global_assignment -name ENABLE_CLOCK_LATENCY ON
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set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
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set_global_assignment -name DEVICE_MIGRATION_LIST "EP2S60F672C5ES,EP2S60F672C5"
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set_location_assignment PIN_AD26 -to led_[7]
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set_location_assignment PIN_AD25 -to led_[6]
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set_location_assignment PIN_AC25 -to led_[5]
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set_location_assignment PIN_AC24 -to led_[4]
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set_location_assignment PIN_AB24 -to led_[3]
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set_location_assignment PIN_AB23 -to led_[2]
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set_location_assignment PIN_AB26 -to led_[1]
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set_location_assignment PIN_AB25 -to led_[0]
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set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
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