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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  Non-restoring unsigned divider                             ////
////                                                             ////
////  Author: Richard Herveille                                  ////
////          richard@asics.ws                                   ////
////          www.asics.ws                                       ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2002 Richard Herveille                        ////
////                    richard@asics.ws                         ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: div_uu.v,v 1.3 2003/09/17 13:08:53 rherveille Exp $
//
//  $Date: 2003/09/17 13:08:53 $
//  $Revision: 1.3 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: div_uu.v,v $
//               Revision 1.3  2003/09/17 13:08:53  rherveille
//               Fixed a bug in the remainder output. Changed a hard value into the required parameter.
//               Fixed a bug in the testbench.
//
//               Revision 1.2  2002/10/31 13:54:58  rherveille
//               Fixed a bug in the remainder output of div_su.v
//
//               Revision 1.1.1.1  2002/10/29 20:29:10  rherveille
//
//
//
 
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
 
module div_uu(clk, ena, z, d, q, s, div0, ovf);
 
        //
        // parameters
        //
        parameter z_width = 16;
        parameter d_width = z_width /2;
 
        //
        // inputs & outputs
        //
        input clk;               // system clock
        input ena;               // clock enable
 
        input  [z_width -1:0] z; // divident
        input  [d_width -1:0] d; // divisor
        output [d_width -1:0] q; // quotient
        output [d_width -1:0] s; // remainder
        output div0;
        output ovf;
        reg [d_width-1:0] q;
        reg [d_width-1:0] s;
        reg div0;
        reg ovf;
 
        //      
        // functions
        //
        function [z_width:0] gen_s;
                input [z_width:0] si;
                input [z_width:0] di;
        begin
          if(si[z_width])
            gen_s = {si[z_width-1:0], 1'b0} + di;
          else
            gen_s = {si[z_width-1:0], 1'b0} - di;
        end
        endfunction
 
        function [d_width-1:0] gen_q;
                input [d_width-1:0] qi;
                input [z_width:0] si;
        begin
          gen_q = {qi[d_width-2:0], ~si[z_width]};
        end
        endfunction
 
        function [d_width-1:0] assign_s;
                input [z_width:0] si;
                input [z_width:0] di;
                reg [z_width:0] tmp;
        begin
          if(si[z_width])
            tmp = si + di;
          else
            tmp = si;
 
          assign_s = tmp[z_width-1:z_width-d_width];
        end
        endfunction
 
        //
        // variables
        //
        reg [d_width-1:0] q_pipe  [d_width-1:0];
        reg [z_width:0] s_pipe  [d_width:0];
        reg [z_width:0] d_pipe  [d_width:0];
 
        reg [d_width:0] div0_pipe, ovf_pipe;
        //
        // perform parameter checks
        //
        // synopsys translate_off
        initial
        begin
          if(d_width !== z_width / 2)
            $display("div.v parameter error (d_width != z_width/2).");
        end
        // synopsys translate_on
 
        integer n0, n1, n2, n3;
 
        // generate divisor (d) pipe
        always @(d)
          d_pipe[0] <= {1'b0, d, {(z_width-d_width){1'b0}} };
 
        always @(posedge clk)
          if(ena)
            for(n0=1; n0 <= d_width; n0=n0+1)
               d_pipe[n0] <= d_pipe[n0-1];
 
        // generate internal remainder pipe
        always @(z)
          s_pipe[0] <= z;
 
        always @(posedge clk)
          if(ena)
            for(n1=1; n1 <= d_width; n1=n1+1)
               s_pipe[n1] <= gen_s(s_pipe[n1-1], d_pipe[n1-1]);
 
        // generate quotient pipe
        always @(posedge clk)
          q_pipe[0] <= 0;
 
        always @(posedge clk)
          if(ena)
            for(n2=1; n2 < d_width; n2=n2+1)
               q_pipe[n2] <= gen_q(q_pipe[n2-1], s_pipe[n2]);
 
 
        // flags (divide_by_zero, overflow)
        always @(z or d)
        begin
          ovf_pipe[0]  <= !(z[z_width-1:d_width] < d);
          div0_pipe[0] <= ~|d;
        end
 
        always @(posedge clk)
          if(ena)
            for(n3=1; n3 <= d_width; n3=n3+1)
            begin
                ovf_pipe[n3] <= ovf_pipe[n3-1];
                div0_pipe[n3] <= div0_pipe[n3-1];
            end
 
        // assign outputs
        always @(posedge clk)
          if(ena)
            ovf <= ovf_pipe[d_width];
 
        always @(posedge clk)
          if(ena)
            div0 <= div0_pipe[d_width];
 
        always @(posedge clk)
          if(ena)
            q <= gen_q(q_pipe[d_width-1], s_pipe[d_width]);
 
        always @(posedge clk)
          if(ena)
            s <= assign_s(s_pipe[d_width], d_pipe[d_width]);
endmodule
 
 
 

Line No.	Rev	Author	Line
1	30	zeus	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Non-restoring unsigned divider ////`
4			`//// ////`
5			`//// Author: Richard Herveille ////`
6			`//// richard@asics.ws ////`
7			`//// www.asics.ws ////`
8			`//// ////`
9			`/////////////////////////////////////////////////////////////////////`
10			`//// ////`
11			`//// Copyright (C) 2002 Richard Herveille ////`
12			`//// richard@asics.ws ////`
13			`//// ////`
14			`//// This source file may be used and distributed without ////`
15			`//// restriction provided that this copyright statement is not ////`
16			`//// removed from the file and that any derivative work contains ////`
17			`//// the original copyright notice and the associated disclaimer.////`
18			`//// ////`
19			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
20			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
21			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
22			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
23			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
24			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
25			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
26			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
27			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
28			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
29			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
30			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
31			`//// POSSIBILITY OF SUCH DAMAGE. ////`
32			`//// ////`
33			`/////////////////////////////////////////////////////////////////////`
34
35			`// CVS Log`
36			`//`
37	52	zeus	`// $Id: div_uu.v,v 1.3 2003/09/17 13:08:53 rherveille Exp $`
38	30	zeus	`//`
39	52	zeus	`// $Date: 2003/09/17 13:08:53 $`
40			`// $Revision: 1.3 $`
41			`// $Author: rherveille $`
42	30	zeus	`// $Locker: $`
43			`// $State: Exp $`
44			`//`
45			`// Change History:`
46	52	zeus	`// $Log: div_uu.v,v $`
47	30	zeus	`// Revision 1.3 2003/09/17 13:08:53 rherveille`
48			`// Fixed a bug in the remainder output. Changed a hard value into the required parameter.`
49			`// Fixed a bug in the testbench.`
50			`//`
51			`// Revision 1.2 2002/10/31 13:54:58 rherveille`
52			`// Fixed a bug in the remainder output of div_su.v`
53			`//`
54			`// Revision 1.1.1.1 2002/10/29 20:29:10 rherveille`
55			`//`
56			`//`
57			`//`
58
59			`//synopsys translate_off`
60			`include "timescale.v"
61			`//synopsys translate_on`
62
63			`module div_uu(clk, ena, z, d, q, s, div0, ovf);`
64
65			`//`
66			`// parameters`
67			`//`
68			`parameter z_width = 16;`
69			`parameter d_width = z_width /2;`
70
71			`//`
72			`// inputs & outputs`
73			`//`
74			`input clk; // system clock`
75			`input ena; // clock enable`
76
77			`input [z_width -1:0] z; // divident`
78			`input [d_width -1:0] d; // divisor`
79			`output [d_width -1:0] q; // quotient`
80			`output [d_width -1:0] s; // remainder`
81			`output div0;`
82			`output ovf;`
83			`reg [d_width-1:0] q;`
84			`reg [d_width-1:0] s;`
85			`reg div0;`
86			`reg ovf;`
87
88			`//`
89			`// functions`
90			`//`
91			`function [z_width:0] gen_s;`
92			`input [z_width:0] si;`
93			`input [z_width:0] di;`
94			`begin`
95			`if(si[z_width])`
96			`gen_s = {si[z_width-1:0], 1'b0} + di;`
97			`else`
98			`gen_s = {si[z_width-1:0], 1'b0} - di;`
99			`end`
100			`endfunction`
101
102			`function [d_width-1:0] gen_q;`
103			`input [d_width-1:0] qi;`
104			`input [z_width:0] si;`
105			`begin`
106			`gen_q = {qi[d_width-2:0], ~si[z_width]};`
107			`end`
108			`endfunction`
109
110			`function [d_width-1:0] assign_s;`
111			`input [z_width:0] si;`
112			`input [z_width:0] di;`
113			`reg [z_width:0] tmp;`
114			`begin`
115			`if(si[z_width])`
116			`tmp = si + di;`
117			`else`
118			`tmp = si;`
119
120			`assign_s = tmp[z_width-1:z_width-d_width];`
121			`end`
122			`endfunction`
123
124			`//`
125			`// variables`
126			`//`
127			`reg [d_width-1:0] q_pipe [d_width-1:0];`
128			`reg [z_width:0] s_pipe [d_width:0];`
129			`reg [z_width:0] d_pipe [d_width:0];`
130
131			`reg [d_width:0] div0_pipe, ovf_pipe;`
132			`//`
133			`// perform parameter checks`
134			`//`
135			`// synopsys translate_off`
136			`initial`
137			`begin`
138			`if(d_width !== z_width / 2)`
139			`$display("div.v parameter error (d_width != z_width/2).");`
140			`end`
141			`// synopsys translate_on`
142
143			`integer n0, n1, n2, n3;`
144
145			`// generate divisor (d) pipe`
146			`always @(d)`
147			`d_pipe[0] <= {1'b0, d, {(z_width-d_width){1'b0}} };`
148
149			`always @(posedge clk)`
150			`if(ena)`
151			`for(n0=1; n0 <= d_width; n0=n0+1)`
152	37	zeus	`d_pipe[n0] <= d_pipe[n0-1];`
153	30	zeus
154			`// generate internal remainder pipe`
155			`always @(z)`
156			`s_pipe[0] <= z;`
157
158			`always @(posedge clk)`
159			`if(ena)`
160			`for(n1=1; n1 <= d_width; n1=n1+1)`
161	37	zeus	`s_pipe[n1] <= gen_s(s_pipe[n1-1], d_pipe[n1-1]);`
162	30	zeus
163			`// generate quotient pipe`
164			`always @(posedge clk)`
165	37	zeus	`q_pipe[0] <= 0;`
166	30	zeus
167			`always @(posedge clk)`
168			`if(ena)`
169			`for(n2=1; n2 < d_width; n2=n2+1)`
170	37	zeus	`q_pipe[n2] <= gen_q(q_pipe[n2-1], s_pipe[n2]);`
171	30	zeus
172
173			`// flags (divide_by_zero, overflow)`
174			`always @(z or d)`
175			`begin`
176			`ovf_pipe[0] <= !(z[z_width-1:d_width] < d);`
177			`div0_pipe[0] <= ~\|d;`
178			`end`
179
180			`always @(posedge clk)`
181			`if(ena)`
182			`for(n3=1; n3 <= d_width; n3=n3+1)`
183			`begin`
184	37	zeus	`ovf_pipe[n3] <= ovf_pipe[n3-1];`
185			`div0_pipe[n3] <= div0_pipe[n3-1];`
186	30	zeus	`end`
187
188			`// assign outputs`
189			`always @(posedge clk)`
190			`if(ena)`
191	37	zeus	`ovf <= ovf_pipe[d_width];`
192	30	zeus
193			`always @(posedge clk)`
194			`if(ena)`
195	37	zeus	`div0 <= div0_pipe[d_width];`
196	30	zeus
197			`always @(posedge clk)`
198			`if(ena)`
199	37	zeus	`q <= gen_q(q_pipe[d_width-1], s_pipe[d_width]);`
200	30	zeus
201			`always @(posedge clk)`
202			`if(ena)`
203	37	zeus	`s <= assign_s(s_pipe[d_width], d_pipe[d_width]);`
204	30	zeus	`endmodule`
205
206
207

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[/] [zet86/] [trunk/] [cores/] [zet/] [rtl/] [util/] [div_uu.v] - Blame information for rev 55