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https://opencores.org/ocsvn/zet86/zet86/trunk
[/] [zet86/] [trunk/] [sim/] [modelsim/] [tb.do] - Blame information for rev 14
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Author |
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1 |
14 |
zeus |
#vdel -all -lib work
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2 |
2 |
zeus |
vlib work
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vlog -work work +incdir+../../rtl-model ../../rtl-model/regfile.v ../../rtl-model/alu.v ../../rtl-model/cpu.v ../../rtl-model/exec.v ../../rtl-model/fetch.v ../../rtl-model/jmp_cond.v ../../rtl-model/util/primitives.v
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vlog -work work +incdir+.. ../memory.v ../testbench.v
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vsim -novopt -t ns work.testbench
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add wave /testbench/clk
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7 |
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add wave /testbench/rst
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8 |
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add wave -radix hexadecimal /testbench/cpu0/fetch0/pc
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9 |
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add wave -radix hexadecimal /testbench/cpu0/fetch0/state
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10 |
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add wave -radix hexadecimal /testbench/cpu0/fetch0/next_state
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11 |
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add wave -radix hexadecimal /testbench/cpu0/fetch0/opcode
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12 |
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add wave -radix hexadecimal /testbench/cpu0/fetch0/modrm
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13 |
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add wave /testbench/cpu0/fetch0/end_seq
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14 |
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add wave -radix hexadecimal sim:/testbench/rd_data
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15 |
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add wave -radix hexadecimal sim:/testbench/wr_data
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16 |
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add wave sim:/testbench/cpu0/fetch0/need_modrm
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17 |
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add wave sim:/testbench/cpu0/fetch0/need_off
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18 |
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add wave sim:/testbench/cpu0/fetch0/need_imm
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19 |
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add wave sim:/testbench/cpu0/fetch0/ir
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20 |
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add wave -radix hexadecimal sim:/testbench/cpu0/fetch0/imm
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21 |
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add wave -radix hexadecimal sim:/testbench/cpu0/fetch0/off
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22 |
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add wave -radix hexadecimal sim:/testbench/addr
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23 |
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add wave -radix hexadecimal sim:/testbench/cpu0/exec0/reg0/r\[15\]
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24 |
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add wave -radix hexadecimal sim:/testbench/cpu0/exec0/reg0/d
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25 |
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add wave sim:/testbench/cpu0/exec0/reg0/addr_a
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26 |
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add wave sim:/testbench/cpu0/exec0/reg0/addr_d
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27 |
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add wave sim:/testbench/cpu0/exec0/reg0/wr
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28 |
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add wave sim:/testbench/we
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29 |
14 |
zeus |
add wave sim:/testbench/ack_i
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30 |
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add wave sim:/testbench/cpu0/fetch_or_exec
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