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Subversion Repositories zet86

[/] [zet86/] [trunk/] [sim/] [modelsim/] [tb.do] - Blame information for rev 2

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Line No. Rev Author Line
1 2 zeus
vdel -all -lib work
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vlib work
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vlog -work work +incdir+../../rtl-model ../../rtl-model/regfile.v ../../rtl-model/alu.v ../../rtl-model/cpu.v ../../rtl-model/exec.v ../../rtl-model/fetch.v ../../rtl-model/jmp_cond.v ../../rtl-model/util/primitives.v
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vlog -work work +incdir+.. ../memory.v ../testbench.v
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vsim -novopt -t ns work.testbench
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add wave /testbench/clk
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add wave /testbench/rst
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add wave -radix hexadecimal /testbench/cpu0/fetch0/pc
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add wave -radix hexadecimal /testbench/cpu0/fetch0/state
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add wave -radix hexadecimal /testbench/cpu0/fetch0/next_state
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add wave -radix hexadecimal /testbench/cpu0/fetch0/opcode
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add wave -radix hexadecimal /testbench/cpu0/fetch0/modrm
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add wave /testbench/cpu0/fetch0/end_seq
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add wave -radix hexadecimal sim:/testbench/rd_data
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add wave -radix hexadecimal sim:/testbench/wr_data
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add wave sim:/testbench/cpu0/fetch0/need_modrm
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add wave sim:/testbench/cpu0/fetch0/need_off
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add wave sim:/testbench/cpu0/fetch0/need_imm
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add wave sim:/testbench/cpu0/fetch0/ir
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add wave -radix hexadecimal sim:/testbench/cpu0/fetch0/imm
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add wave -radix hexadecimal sim:/testbench/cpu0/fetch0/off
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add wave -radix hexadecimal sim:/testbench/addr
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add wave -radix hexadecimal sim:/testbench/cpu0/exec0/reg0/r\[15\]
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add wave -radix hexadecimal sim:/testbench/cpu0/exec0/reg0/d
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add wave sim:/testbench/cpu0/exec0/reg0/addr_a
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add wave sim:/testbench/cpu0/exec0/reg0/addr_d
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add wave sim:/testbench/cpu0/exec0/reg0/wr
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add wave sim:/testbench/we
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add wave sim:/testbench/cpu0/fetch_or_exec

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