| 1 |
28 |
zeus |
vdel -all -lib work
|
| 2 |
|
|
vlib work
|
| 3 |
|
|
vlog -work work -lint +incdir+../../rtl-model ../../rtl-model/regfile.v ../../rtl-model/alu.v ../../rtl-model/cpu.v ../../rtl-model/exec.v ../../rtl-model/fetch.v ../../rtl-model/jmp_cond.v ../../rtl-model/util/primitives.v ../../rtl-model/rotate.v
|
| 4 |
|
|
vlog -work work +incdir+.. ../memory.v ../testbench.v
|
| 5 |
2 |
zeus |
vsim -novopt -t ns work.testbench
|
| 6 |
22 |
zeus |
add wave -label clk /testbench/clk
|
| 7 |
|
|
add wave -label rst /testbench/rst
|
| 8 |
|
|
add wave -label pc -radix hexadecimal /testbench/cpu0/fetch0/pc
|
| 9 |
|
|
add wave -divider fetch
|
| 10 |
|
|
add wave -label state -radix hexadecimal /testbench/cpu0/fetch0/state
|
| 11 |
|
|
add wave -label next_state -radix hexadecimal /testbench/cpu0/fetch0/next_state
|
| 12 |
|
|
add wave -label opcode -radix hexadecimal /testbench/cpu0/fetch0/opcode
|
| 13 |
|
|
add wave -label modrm -radix hexadecimal /testbench/cpu0/fetch0/modrm
|
| 14 |
|
|
add wave -label seq_addr /testbench/cpu0/fetch0/decode0/seq_addr
|
| 15 |
|
|
add wave -label end_seq /testbench/cpu0/fetch0/end_seq
|
| 16 |
|
|
add wave -label need_modrm /testbench/cpu0/fetch0/need_modrm
|
| 17 |
|
|
add wave -label need_off /testbench/cpu0/fetch0/need_off
|
| 18 |
|
|
add wave -label need_imm /testbench/cpu0/fetch0/need_imm
|
| 19 |
|
|
add wave -label ir /testbench/cpu0/fetch0/ir
|
| 20 |
|
|
add wave -label imm -radix hexadecimal /testbench/cpu0/fetch0/imm
|
| 21 |
|
|
add wave -label off -radix hexadecimal /testbench/cpu0/fetch0/off
|
| 22 |
|
|
add wave -divider alu
|
| 23 |
|
|
add wave -label x -radix hexadecimal /testbench/cpu0/exec0/a
|
| 24 |
|
|
add wave -label y -radix hexadecimal /testbench/cpu0/exec0/bus_b
|
| 25 |
24 |
zeus |
add wave -label t -radix hexadecimal /testbench/cpu0/exec0/alu0/t
|
| 26 |
|
|
add wave -label func -radix hexadecimal /testbench/cpu0/exec0/alu0/func
|
| 27 |
22 |
zeus |
add wave -label rd_data -radix hexadecimal sim:/testbench/rd_data
|
| 28 |
|
|
add wave -label wr_data -radix hexadecimal sim:/testbench/wr_data
|
| 29 |
|
|
add wave -label addr -radix hexadecimal /testbench/addr
|
| 30 |
|
|
add wave -label r\[15\] -radix hexadecimal /testbench/cpu0/exec0/reg0/r\[15\]
|
| 31 |
|
|
add wave -label d -radix hexadecimal /testbench/cpu0/exec0/reg0/d
|
| 32 |
|
|
add wave -label addr_a /testbench/cpu0/exec0/reg0/addr_a
|
| 33 |
|
|
add wave -label addr_d /testbench/cpu0/exec0/reg0/addr_d
|
| 34 |
|
|
add wave -label wr /testbench/cpu0/exec0/reg0/wr
|
| 35 |
|
|
add wave -label we /testbench/we
|
| 36 |
|
|
add wave -label ack_i /testbench/ack_i
|
| 37 |
|
|
add wave -label fetch_or_exec /testbench/cpu0/fetch_or_exec
|
| 38 |
28 |
zeus |
#run 50us
|
