1 |
28 |
zeus |
vdel -all -lib work
|
2 |
29 |
zeus |
vmap unisims /opt/Xilinx/10.1/modelsim/verilog/unisims
|
3 |
28 |
zeus |
vlib work
|
4 |
30 |
zeus |
vlog -work work -lint +incdir+../../rtl-model +incdir+.. ../../rtl-model/regfile.v ../../rtl-model/alu.v ../../rtl-model/cpu.v ../../rtl-model/exec.v ../../rtl-model/fetch.v ../../rtl-model/jmp_cond.v ../../rtl-model/util/primitives.v ../../rtl-model/util/div_su.v ../../rtl-model/util/div_uu.v ../../rtl-model/rotate.v
|
5 |
29 |
zeus |
vlog -work work +incdir+.. ../memory.v ../testbench.v ../mult.v
|
6 |
|
|
vlog -work unisims /opt/Xilinx/10.1/ISE/verilog/src/glbl.v
|
7 |
|
|
vsim -L /opt/Xilinx/10.1/modelsim/verilog/unisims -novopt -t ns work.testbench work.glbl
|
8 |
22 |
zeus |
add wave -label clk /testbench/clk
|
9 |
|
|
add wave -label rst /testbench/rst
|
10 |
|
|
add wave -label pc -radix hexadecimal /testbench/cpu0/fetch0/pc
|
11 |
|
|
add wave -divider fetch
|
12 |
|
|
add wave -label state -radix hexadecimal /testbench/cpu0/fetch0/state
|
13 |
|
|
add wave -label next_state -radix hexadecimal /testbench/cpu0/fetch0/next_state
|
14 |
|
|
add wave -label opcode -radix hexadecimal /testbench/cpu0/fetch0/opcode
|
15 |
|
|
add wave -label modrm -radix hexadecimal /testbench/cpu0/fetch0/modrm
|
16 |
|
|
add wave -label seq_addr /testbench/cpu0/fetch0/decode0/seq_addr
|
17 |
|
|
add wave -label end_seq /testbench/cpu0/fetch0/end_seq
|
18 |
|
|
add wave -label need_modrm /testbench/cpu0/fetch0/need_modrm
|
19 |
|
|
add wave -label need_off /testbench/cpu0/fetch0/need_off
|
20 |
|
|
add wave -label need_imm /testbench/cpu0/fetch0/need_imm
|
21 |
|
|
add wave -label ir /testbench/cpu0/fetch0/ir
|
22 |
|
|
add wave -label imm -radix hexadecimal /testbench/cpu0/fetch0/imm
|
23 |
|
|
add wave -label off -radix hexadecimal /testbench/cpu0/fetch0/off
|
24 |
|
|
add wave -divider alu
|
25 |
|
|
add wave -label x -radix hexadecimal /testbench/cpu0/exec0/a
|
26 |
|
|
add wave -label y -radix hexadecimal /testbench/cpu0/exec0/bus_b
|
27 |
24 |
zeus |
add wave -label t -radix hexadecimal /testbench/cpu0/exec0/alu0/t
|
28 |
|
|
add wave -label func -radix hexadecimal /testbench/cpu0/exec0/alu0/func
|
29 |
22 |
zeus |
add wave -label rd_data -radix hexadecimal sim:/testbench/rd_data
|
30 |
|
|
add wave -label wr_data -radix hexadecimal sim:/testbench/wr_data
|
31 |
|
|
add wave -label addr -radix hexadecimal /testbench/addr
|
32 |
|
|
add wave -label r\[15\] -radix hexadecimal /testbench/cpu0/exec0/reg0/r\[15\]
|
33 |
|
|
add wave -label d -radix hexadecimal /testbench/cpu0/exec0/reg0/d
|
34 |
|
|
add wave -label addr_a /testbench/cpu0/exec0/reg0/addr_a
|
35 |
|
|
add wave -label addr_d /testbench/cpu0/exec0/reg0/addr_d
|
36 |
|
|
add wave -label wr /testbench/cpu0/exec0/reg0/wr
|
37 |
|
|
add wave -label we /testbench/we
|
38 |
|
|
add wave -label ack_i /testbench/ack_i
|
39 |
|
|
add wave -label fetch_or_exec /testbench/cpu0/fetch_or_exec
|
40 |
30 |
zeus |
add wave -divider mul
|
41 |
|
|
add wave -radix hexadecimal -r /testbench/cpu0/exec0/alu0/mul3/dut/*
|
42 |
28 |
zeus |
#run 50us
|