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[/] [zet86/] [trunk/] [sim/] [signmul17.v] - Blame information for rev 52

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module signmul17 (
    input clk,
 
    input      signed [16:0] a,
    input      signed [16:0] b,
    output reg signed [33:0] p
  );
 
  // Behaviour
  always @(posedge clk) p <= a * b;
endmodule

Line No.	Rev	Author	Line
1	52	zeus	`module signmul17 (`
2			`input clk,`
3
4			`input signed [16:0] a,`
5			`input signed [16:0] b,`
6			`output reg signed [33:0] p`
7			`);`
8
9			`// Behaviour`
10			`always @(posedge clk) p <= a * b;`
11			`endmodule`

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[/] [zet86/] [trunk/] [sim/] [signmul17.v] - Blame information for rev 52