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[/] [zet86/] [trunk/] [sim/] [signmul17.v] - Blame information for rev 55

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1 52 zeus
module signmul17 (
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    input clk,
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    input      signed [16:0] a,
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    input      signed [16:0] b,
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    output reg signed [33:0] p
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  );
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  // Behaviour
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  always @(posedge clk) p <= a * b;
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endmodule

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