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[/] [zet86/] [trunk/] [soc/] [but_int.v] - Blame information for rev 49

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module but_int (
    input      clk,
    input      rst,
    input      but_,
    output reg intr,
    input      inta
  );
 
  // Register declaration
  reg old_but;
 
  // Behaviour
  always @(posedge clk)
    if (rst) intr <= 1'b0;
    else intr <= intr ? !inta : (but_ && !old_but);
 
  always @(posedge clk) old_but <= but_;
 
endmodule

Line No.	Rev	Author	Line
1	42	zeus	`module but_int (`
2			`input clk,`
3			`input rst,`
4			`input but_,`
5			`output reg intr,`
6			`input inta`
7			`);`
8
9			`// Register declaration`
10			`reg old_but;`
11
12			`// Behaviour`
13			`always @(posedge clk)`
14			`if (rst) intr <= 1'b0;`
15			`else intr <= intr ? !inta : (but_ && !old_but);`
16
17			`always @(posedge clk) old_but <= but_;`
18
19			`endmodule`

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[/] [zet86/] [trunk/] [soc/] [but_int.v] - Blame information for rev 49