| 1 |
43 |
zeus |
/*
|
| 2 |
|
|
* PS2 Wishbone 8042 compatible keyboard controller
|
| 3 |
|
|
*
|
| 4 |
|
|
* Copyright (c) 2009 Zeus Gomez Marmolejo <zeus@opencores.org>
|
| 5 |
|
|
* adapted from the opencores keyboard controller from John Clayton
|
| 6 |
|
|
*
|
| 7 |
|
|
* This file is part of the Zet processor. This processor is free
|
| 8 |
|
|
* hardware; you can redistribute it and/or modify it under the terms of
|
| 9 |
|
|
* the GNU General Public License as published by the Free Software
|
| 10 |
|
|
* Foundation; either version 3, or (at your option) any later version.
|
| 11 |
|
|
*
|
| 12 |
|
|
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
|
| 13 |
|
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
| 14 |
|
|
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
| 15 |
|
|
* License for more details.
|
| 16 |
|
|
*
|
| 17 |
|
|
* You should have received a copy of the GNU General Public License
|
| 18 |
|
|
* along with Zet; see the file COPYING. If not, see
|
| 19 |
|
|
* <http://www.gnu.org/licenses/>.
|
| 20 |
|
|
*/
|
| 21 |
|
|
|
| 22 |
52 |
zeus |
`include "defines.v"
|
| 23 |
|
|
|
| 24 |
43 |
zeus |
`timescale 1ns/100ps
|
| 25 |
|
|
|
| 26 |
|
|
`define TOTAL_BITS 11
|
| 27 |
|
|
`define RELEASE_CODE 16'hF0
|
| 28 |
|
|
`define LEFT_SHIFT 16'h12
|
| 29 |
|
|
`define RIGHT_SHIFT 16'h59
|
| 30 |
|
|
|
| 31 |
|
|
module ps2_keyb (
|
| 32 |
52 |
zeus |
`ifdef DEBUG
|
| 33 |
|
|
output rx_output_strobe,
|
| 34 |
|
|
output released,
|
| 35 |
|
|
output rx_shifting_done,
|
| 36 |
|
|
`endif
|
| 37 |
43 |
zeus |
// Wishbone slave interface
|
| 38 |
|
|
input wb_clk_i,
|
| 39 |
|
|
input wb_rst_i,
|
| 40 |
|
|
output reg [7:0] wb_dat_o, // scancode
|
| 41 |
|
|
output reg wb_tgc_o, // intr
|
| 42 |
|
|
|
| 43 |
|
|
// PS2 PAD signals
|
| 44 |
|
|
inout ps2_clk_,
|
| 45 |
|
|
inout ps2_data_
|
| 46 |
|
|
);
|
| 47 |
|
|
|
| 48 |
|
|
// Parameter declarations
|
| 49 |
|
|
// The timer value can be up to (2^bits) inclusive.
|
| 50 |
|
|
parameter TIMER_60USEC_VALUE_PP = 1920; // Number of sys_clks for 60usec.
|
| 51 |
|
|
parameter TIMER_60USEC_BITS_PP = 11; // Number of bits needed for timer
|
| 52 |
|
|
parameter TIMER_5USEC_VALUE_PP = 186; // Number of sys_clks for debounce
|
| 53 |
|
|
parameter TIMER_5USEC_BITS_PP = 8; // Number of bits needed for timer
|
| 54 |
|
|
parameter TRAP_SHIFT_KEYS_PP = 0; // Default: No shift key trap.
|
| 55 |
|
|
|
| 56 |
|
|
// State encodings, provided as parameters
|
| 57 |
|
|
// for flexibility to the one instantiating the module.
|
| 58 |
|
|
// In general, the default values need not be changed.
|
| 59 |
|
|
|
| 60 |
|
|
// State "m1_rx_clk_l" has been chosen on purpose. Since the input
|
| 61 |
|
|
// synchronizing flip-flops initially contain zero, it takes one clk
|
| 62 |
|
|
// for them to update to reflect the actual (idle = high) status of
|
| 63 |
|
|
// the I/O lines from the keyboard. Therefore, choosing 0 for m1_rx_clk_l
|
| 64 |
|
|
// allows the state machine to transition to m1_rx_clk_h when the true
|
| 65 |
|
|
// values of the input signals become present at the outputs of the
|
| 66 |
|
|
// synchronizing flip-flops. This initial transition is harmless, and it
|
| 67 |
|
|
// eliminates the need for a "reset" pulse before the interface can operate.
|
| 68 |
|
|
parameter m1_rx_clk_h = 1;
|
| 69 |
|
|
parameter m1_rx_clk_l = 0;
|
| 70 |
|
|
parameter m1_rx_falling_edge_marker = 13;
|
| 71 |
|
|
parameter m1_rx_rising_edge_marker = 14;
|
| 72 |
|
|
parameter m1_tx_force_clk_l = 3;
|
| 73 |
|
|
parameter m1_tx_first_wait_clk_h = 10;
|
| 74 |
|
|
parameter m1_tx_first_wait_clk_l = 11;
|
| 75 |
|
|
parameter m1_tx_reset_timer = 12;
|
| 76 |
|
|
parameter m1_tx_wait_clk_h = 2;
|
| 77 |
|
|
parameter m1_tx_clk_h = 4;
|
| 78 |
|
|
parameter m1_tx_clk_l = 5;
|
| 79 |
|
|
parameter m1_tx_wait_keyboard_ack = 6;
|
| 80 |
|
|
parameter m1_tx_done_recovery = 7;
|
| 81 |
|
|
parameter m1_tx_error_no_keyboard_ack = 8;
|
| 82 |
|
|
parameter m1_tx_rising_edge_marker = 9;
|
| 83 |
|
|
|
| 84 |
|
|
// Nets and registers
|
| 85 |
|
|
wire rx_output_event;
|
| 86 |
|
|
wire tx_shifting_done;
|
| 87 |
|
|
wire timer_60usec_done;
|
| 88 |
|
|
wire timer_5usec_done;
|
| 89 |
52 |
zeus |
`ifndef DEBUG
|
| 90 |
|
|
wire rx_output_strobe;
|
| 91 |
|
|
wire rx_shifting_done;
|
| 92 |
43 |
zeus |
wire released;
|
| 93 |
52 |
zeus |
`endif
|
| 94 |
43 |
zeus |
wire [6:0] xt_code;
|
| 95 |
|
|
|
| 96 |
|
|
reg [3:0] bit_count;
|
| 97 |
|
|
reg [3:0] m1_state;
|
| 98 |
|
|
reg [3:0] m1_next_state;
|
| 99 |
|
|
|
| 100 |
|
|
reg ps2_clk_hi_z; // Without keyboard, high Z equals 1 due to pullups.
|
| 101 |
|
|
reg ps2_data_hi_z; // Without keyboard, high Z equals 1 due to pullups.
|
| 102 |
|
|
reg ps2_clk_s; // Synchronous version of this input
|
| 103 |
|
|
reg ps2_data_s; // Synchronous version of this input
|
| 104 |
|
|
|
| 105 |
|
|
reg enable_timer_60usec;
|
| 106 |
|
|
reg enable_timer_5usec;
|
| 107 |
|
|
reg [TIMER_60USEC_BITS_PP-1:0] timer_60usec_count;
|
| 108 |
|
|
reg [TIMER_5USEC_BITS_PP-1:0] timer_5usec_count;
|
| 109 |
|
|
|
| 110 |
|
|
reg [`TOTAL_BITS-1:0] q;
|
| 111 |
|
|
|
| 112 |
|
|
reg hold_released; // Holds prior value, cleared at rx_output_strobe
|
| 113 |
|
|
|
| 114 |
|
|
// Module instantiation
|
| 115 |
|
|
translate_8042 tr0 (
|
| 116 |
|
|
.at_code (q[7:1]),
|
| 117 |
|
|
.xt_code (xt_code)
|
| 118 |
|
|
);
|
| 119 |
|
|
|
| 120 |
|
|
// Continuous assignments
|
| 121 |
|
|
// This signal is high for one clock at the end of the timer count.
|
| 122 |
|
|
assign rx_shifting_done = (bit_count == `TOTAL_BITS);
|
| 123 |
|
|
assign tx_shifting_done = (bit_count == `TOTAL_BITS-1);
|
| 124 |
|
|
|
| 125 |
|
|
assign rx_output_event = (rx_shifting_done
|
| 126 |
|
|
&& ~released
|
| 127 |
|
|
);
|
| 128 |
|
|
assign rx_output_strobe = (rx_shifting_done
|
| 129 |
|
|
&& ~released
|
| 130 |
|
|
&& ( (TRAP_SHIFT_KEYS_PP == 0)
|
| 131 |
|
|
|| ( (q[8:1] != `RIGHT_SHIFT)
|
| 132 |
|
|
&&(q[8:1] != `LEFT_SHIFT)
|
| 133 |
|
|
)
|
| 134 |
|
|
)
|
| 135 |
|
|
);
|
| 136 |
|
|
|
| 137 |
|
|
assign ps2_clk_ = ps2_clk_hi_z ? 1'bZ : 1'b0;
|
| 138 |
|
|
assign ps2_data_ = ps2_data_hi_z ? 1'bZ : 1'b0;
|
| 139 |
|
|
|
| 140 |
|
|
assign timer_60usec_done =
|
| 141 |
|
|
(timer_60usec_count == (TIMER_60USEC_VALUE_PP - 1));
|
| 142 |
|
|
assign timer_5usec_done = (timer_5usec_count == TIMER_5USEC_VALUE_PP - 1);
|
| 143 |
|
|
|
| 144 |
|
|
// Create the signals which indicate special scan codes received.
|
| 145 |
|
|
// These are the "unlatched versions."
|
| 146 |
|
|
//assign extended = (q[8:1] == `EXTEND_CODE) && rx_shifting_done;
|
| 147 |
|
|
assign released = (q[8:1] == `RELEASE_CODE) && rx_shifting_done;
|
| 148 |
|
|
|
| 149 |
|
|
// Behaviour
|
| 150 |
52 |
zeus |
// wb_tgc_o
|
| 151 |
43 |
zeus |
always @(posedge wb_clk_i)
|
| 152 |
52 |
zeus |
wb_tgc_o <= wb_rst_i ? 1'b0 : rx_output_strobe;
|
| 153 |
43 |
zeus |
|
| 154 |
|
|
// This is the shift register
|
| 155 |
|
|
always @(posedge wb_clk_i)
|
| 156 |
|
|
if (wb_rst_i) q <= 0;
|
| 157 |
|
|
// else if (((m1_state == m1_rx_clk_h) && ~ps2_clk_s)
|
| 158 |
|
|
else if ( (m1_state == m1_rx_falling_edge_marker)
|
| 159 |
|
|
||(m1_state == m1_tx_rising_edge_marker) )
|
| 160 |
|
|
q <= {ps2_data_s,q[`TOTAL_BITS-1:1]};
|
| 161 |
|
|
|
| 162 |
|
|
// This is the 60usec timer counter
|
| 163 |
|
|
always @(posedge wb_clk_i)
|
| 164 |
|
|
if (~enable_timer_60usec) timer_60usec_count <= 0;
|
| 165 |
|
|
else if (~timer_60usec_done) timer_60usec_count <= timer_60usec_count + 1;
|
| 166 |
|
|
|
| 167 |
|
|
// This is the 5usec timer counter
|
| 168 |
|
|
always @(posedge wb_clk_i)
|
| 169 |
|
|
if (~enable_timer_5usec) timer_5usec_count <= 0;
|
| 170 |
|
|
else if (~timer_5usec_done) timer_5usec_count <= timer_5usec_count + 1;
|
| 171 |
|
|
|
| 172 |
|
|
// Input "synchronizing" logic -- synchronizes the inputs to the state
|
| 173 |
|
|
// machine clock, thus avoiding errors related to
|
| 174 |
|
|
// spurious state machine transitions.
|
| 175 |
|
|
//
|
| 176 |
|
|
// Since the initial state of registers is zero, and the idle state
|
| 177 |
|
|
// of the ps2_clk and ps2_data lines is "1" (due to pullups), the
|
| 178 |
|
|
// "sense" of the ps2_clk_s signal is inverted from the true signal.
|
| 179 |
|
|
// This allows the state machine to "come up" in the correct
|
| 180 |
|
|
always @(posedge wb_clk_i)
|
| 181 |
|
|
begin
|
| 182 |
|
|
ps2_clk_s <= ps2_clk_;
|
| 183 |
|
|
ps2_data_s <= ps2_data_;
|
| 184 |
|
|
end
|
| 185 |
|
|
|
| 186 |
|
|
// State transition logic
|
| 187 |
|
|
always @(m1_state
|
| 188 |
|
|
or q
|
| 189 |
|
|
or tx_shifting_done
|
| 190 |
|
|
or ps2_clk_s
|
| 191 |
|
|
or ps2_data_s
|
| 192 |
|
|
or timer_60usec_done
|
| 193 |
|
|
or timer_5usec_done
|
| 194 |
|
|
)
|
| 195 |
|
|
begin : m1_state_logic
|
| 196 |
|
|
|
| 197 |
|
|
// Output signals default to this value,
|
| 198 |
|
|
// unless changed in a state condition.
|
| 199 |
|
|
ps2_clk_hi_z <= 1;
|
| 200 |
|
|
ps2_data_hi_z <= 1;
|
| 201 |
|
|
enable_timer_60usec <= 0;
|
| 202 |
|
|
enable_timer_5usec <= 0;
|
| 203 |
|
|
|
| 204 |
|
|
case (m1_state)
|
| 205 |
|
|
|
| 206 |
|
|
m1_rx_clk_h :
|
| 207 |
|
|
begin
|
| 208 |
|
|
enable_timer_60usec <= 1;
|
| 209 |
|
|
if (~ps2_clk_s)
|
| 210 |
|
|
m1_next_state <= m1_rx_falling_edge_marker;
|
| 211 |
|
|
else m1_next_state <= m1_rx_clk_h;
|
| 212 |
|
|
end
|
| 213 |
|
|
|
| 214 |
|
|
m1_rx_falling_edge_marker :
|
| 215 |
|
|
begin
|
| 216 |
|
|
enable_timer_60usec <= 0;
|
| 217 |
|
|
m1_next_state <= m1_rx_clk_l;
|
| 218 |
|
|
end
|
| 219 |
|
|
|
| 220 |
|
|
m1_rx_rising_edge_marker :
|
| 221 |
|
|
begin
|
| 222 |
|
|
enable_timer_60usec <= 0;
|
| 223 |
|
|
m1_next_state <= m1_rx_clk_h;
|
| 224 |
|
|
end
|
| 225 |
|
|
|
| 226 |
|
|
m1_rx_clk_l :
|
| 227 |
|
|
begin
|
| 228 |
|
|
enable_timer_60usec <= 1;
|
| 229 |
|
|
if (ps2_clk_s)
|
| 230 |
|
|
m1_next_state <= m1_rx_rising_edge_marker;
|
| 231 |
|
|
else m1_next_state <= m1_rx_clk_l;
|
| 232 |
|
|
end
|
| 233 |
|
|
|
| 234 |
|
|
m1_tx_reset_timer :
|
| 235 |
|
|
begin
|
| 236 |
|
|
enable_timer_60usec <= 0;
|
| 237 |
|
|
m1_next_state <= m1_tx_force_clk_l;
|
| 238 |
|
|
end
|
| 239 |
|
|
|
| 240 |
|
|
m1_tx_force_clk_l :
|
| 241 |
|
|
begin
|
| 242 |
|
|
enable_timer_60usec <= 1;
|
| 243 |
|
|
ps2_clk_hi_z <= 0; // Force the ps2_clk line low.
|
| 244 |
|
|
if (timer_60usec_done)
|
| 245 |
|
|
m1_next_state <= m1_tx_first_wait_clk_h;
|
| 246 |
|
|
else m1_next_state <= m1_tx_force_clk_l;
|
| 247 |
|
|
end
|
| 248 |
|
|
|
| 249 |
|
|
m1_tx_first_wait_clk_h :
|
| 250 |
|
|
begin
|
| 251 |
|
|
enable_timer_5usec <= 1;
|
| 252 |
|
|
ps2_data_hi_z <= 0; // Start bit.
|
| 253 |
|
|
if (~ps2_clk_s && timer_5usec_done)
|
| 254 |
|
|
m1_next_state <= m1_tx_clk_l;
|
| 255 |
|
|
else
|
| 256 |
|
|
m1_next_state <= m1_tx_first_wait_clk_h;
|
| 257 |
|
|
end
|
| 258 |
|
|
|
| 259 |
|
|
// This state must be included because the device might possibly
|
| 260 |
|
|
// delay for up to 10 milliseconds before beginning its clock pulses.
|
| 261 |
|
|
// During that waiting time, we cannot drive the data (q[0]) because it
|
| 262 |
|
|
// is possibly 1, which would cause the keyboard to abort its receive
|
| 263 |
|
|
// and the expected clocks would then never be generated.
|
| 264 |
|
|
m1_tx_first_wait_clk_l :
|
| 265 |
|
|
begin
|
| 266 |
|
|
ps2_data_hi_z <= 0;
|
| 267 |
|
|
if (~ps2_clk_s) m1_next_state <= m1_tx_clk_l;
|
| 268 |
|
|
else m1_next_state <= m1_tx_first_wait_clk_l;
|
| 269 |
|
|
end
|
| 270 |
|
|
|
| 271 |
|
|
m1_tx_wait_clk_h :
|
| 272 |
|
|
begin
|
| 273 |
|
|
enable_timer_5usec <= 1;
|
| 274 |
|
|
ps2_data_hi_z <= q[0];
|
| 275 |
|
|
if (ps2_clk_s && timer_5usec_done)
|
| 276 |
|
|
m1_next_state <= m1_tx_rising_edge_marker;
|
| 277 |
|
|
else
|
| 278 |
|
|
m1_next_state <= m1_tx_wait_clk_h;
|
| 279 |
|
|
end
|
| 280 |
|
|
|
| 281 |
|
|
m1_tx_rising_edge_marker :
|
| 282 |
|
|
begin
|
| 283 |
|
|
ps2_data_hi_z <= q[0];
|
| 284 |
|
|
m1_next_state <= m1_tx_clk_h;
|
| 285 |
|
|
end
|
| 286 |
|
|
|
| 287 |
|
|
m1_tx_clk_h :
|
| 288 |
|
|
begin
|
| 289 |
|
|
ps2_data_hi_z <= q[0];
|
| 290 |
|
|
if (tx_shifting_done) m1_next_state <= m1_tx_wait_keyboard_ack;
|
| 291 |
|
|
else if (~ps2_clk_s) m1_next_state <= m1_tx_clk_l;
|
| 292 |
|
|
else m1_next_state <= m1_tx_clk_h;
|
| 293 |
|
|
end
|
| 294 |
|
|
|
| 295 |
|
|
m1_tx_clk_l :
|
| 296 |
|
|
begin
|
| 297 |
|
|
ps2_data_hi_z <= q[0];
|
| 298 |
|
|
if (ps2_clk_s) m1_next_state <= m1_tx_wait_clk_h;
|
| 299 |
|
|
else m1_next_state <= m1_tx_clk_l;
|
| 300 |
|
|
end
|
| 301 |
|
|
|
| 302 |
|
|
m1_tx_wait_keyboard_ack :
|
| 303 |
|
|
begin
|
| 304 |
|
|
if (~ps2_clk_s && ps2_data_s)
|
| 305 |
|
|
m1_next_state <= m1_tx_error_no_keyboard_ack;
|
| 306 |
|
|
else if (~ps2_clk_s && ~ps2_data_s)
|
| 307 |
|
|
m1_next_state <= m1_tx_done_recovery;
|
| 308 |
|
|
else m1_next_state <= m1_tx_wait_keyboard_ack;
|
| 309 |
|
|
end
|
| 310 |
|
|
|
| 311 |
|
|
m1_tx_done_recovery :
|
| 312 |
|
|
begin
|
| 313 |
|
|
if (ps2_clk_s && ps2_data_s) m1_next_state <= m1_rx_clk_h;
|
| 314 |
|
|
else m1_next_state <= m1_tx_done_recovery;
|
| 315 |
|
|
end
|
| 316 |
|
|
|
| 317 |
|
|
m1_tx_error_no_keyboard_ack :
|
| 318 |
|
|
begin
|
| 319 |
|
|
if (ps2_clk_s && ps2_data_s) m1_next_state <= m1_rx_clk_h;
|
| 320 |
|
|
else m1_next_state <= m1_tx_error_no_keyboard_ack;
|
| 321 |
|
|
end
|
| 322 |
|
|
|
| 323 |
|
|
default : m1_next_state <= m1_rx_clk_h;
|
| 324 |
|
|
endcase
|
| 325 |
|
|
end
|
| 326 |
|
|
|
| 327 |
|
|
// State register
|
| 328 |
|
|
always @(posedge wb_clk_i)
|
| 329 |
|
|
begin : m1_state_register
|
| 330 |
|
|
if (wb_rst_i) m1_state <= m1_rx_clk_h;
|
| 331 |
|
|
else m1_state <= m1_next_state;
|
| 332 |
|
|
end
|
| 333 |
|
|
|
| 334 |
|
|
// wb_dat_o - scancode
|
| 335 |
|
|
always @(posedge wb_clk_i)
|
| 336 |
|
|
if (wb_rst_i) wb_dat_o <= 8'b0;
|
| 337 |
|
|
else wb_dat_o <=
|
| 338 |
|
|
(rx_output_strobe && q[8:1]) ? (q[8] ? q[8:1]
|
| 339 |
|
|
: {hold_released,xt_code})
|
| 340 |
|
|
: wb_dat_o;
|
| 341 |
|
|
|
| 342 |
|
|
// This is the bit counter
|
| 343 |
|
|
always @(posedge wb_clk_i)
|
| 344 |
|
|
begin
|
| 345 |
|
|
if (wb_rst_i
|
| 346 |
|
|
|| rx_shifting_done
|
| 347 |
|
|
|| (m1_state == m1_tx_wait_keyboard_ack) // After tx is done.
|
| 348 |
|
|
) bit_count <= 0; // normal reset
|
| 349 |
|
|
else if (timer_60usec_done
|
| 350 |
|
|
&& (m1_state == m1_rx_clk_h)
|
| 351 |
|
|
&& (ps2_clk_s)
|
| 352 |
|
|
) bit_count <= 0; // rx watchdog timer reset
|
| 353 |
|
|
else if ( (m1_state == m1_rx_falling_edge_marker) // increment for rx
|
| 354 |
|
|
||(m1_state == m1_tx_rising_edge_marker) // increment for tx
|
| 355 |
|
|
)
|
| 356 |
|
|
bit_count <= bit_count + 1;
|
| 357 |
|
|
end
|
| 358 |
|
|
|
| 359 |
|
|
// Store the special scan code status bits
|
| 360 |
|
|
// Not the final output, but an intermediate storage place,
|
| 361 |
|
|
// until the entire set of output data can be assembled.
|
| 362 |
|
|
always @(posedge wb_clk_i)
|
| 363 |
|
|
if (wb_rst_i || rx_output_event) hold_released <= 0;
|
| 364 |
|
|
else if (rx_shifting_done && released) hold_released <= 1;
|
| 365 |
|
|
|
| 366 |
|
|
endmodule
|
| 367 |
|
|
|
| 368 |
|
|
|
| 369 |
|
|
module translate_8042 (
|
| 370 |
|
|
input [6:0] at_code,
|
| 371 |
|
|
output reg [6:0] xt_code
|
| 372 |
|
|
);
|
| 373 |
|
|
|
| 374 |
|
|
// Behaviour
|
| 375 |
|
|
always @(at_code)
|
| 376 |
|
|
case (at_code)
|
| 377 |
|
|
7'h00: xt_code <= 7'h7f;
|
| 378 |
|
|
7'h01: xt_code <= 7'h43;
|
| 379 |
|
|
7'h02: xt_code <= 7'h41;
|
| 380 |
|
|
7'h03: xt_code <= 7'h3f;
|
| 381 |
|
|
7'h04: xt_code <= 7'h3d;
|
| 382 |
|
|
7'h05: xt_code <= 7'h3b;
|
| 383 |
|
|
7'h06: xt_code <= 7'h3c;
|
| 384 |
|
|
7'h07: xt_code <= 7'h58;
|
| 385 |
|
|
7'h08: xt_code <= 7'h64;
|
| 386 |
|
|
7'h09: xt_code <= 7'h44;
|
| 387 |
|
|
7'h0a: xt_code <= 7'h42;
|
| 388 |
|
|
7'h0b: xt_code <= 7'h40;
|
| 389 |
|
|
7'h0c: xt_code <= 7'h3e;
|
| 390 |
|
|
7'h0d: xt_code <= 7'h0f;
|
| 391 |
|
|
7'h0e: xt_code <= 7'h29;
|
| 392 |
|
|
7'h0f: xt_code <= 7'h59;
|
| 393 |
|
|
7'h10: xt_code <= 7'h65;
|
| 394 |
|
|
7'h11: xt_code <= 7'h38;
|
| 395 |
|
|
7'h12: xt_code <= 7'h2a;
|
| 396 |
|
|
7'h13: xt_code <= 7'h70;
|
| 397 |
|
|
7'h14: xt_code <= 7'h1d;
|
| 398 |
|
|
7'h15: xt_code <= 7'h10;
|
| 399 |
|
|
7'h16: xt_code <= 7'h02;
|
| 400 |
|
|
7'h17: xt_code <= 7'h5a;
|
| 401 |
|
|
7'h18: xt_code <= 7'h66;
|
| 402 |
|
|
7'h19: xt_code <= 7'h71;
|
| 403 |
|
|
7'h1a: xt_code <= 7'h2c;
|
| 404 |
|
|
7'h1b: xt_code <= 7'h1f;
|
| 405 |
|
|
7'h1c: xt_code <= 7'h1e;
|
| 406 |
|
|
7'h1d: xt_code <= 7'h11;
|
| 407 |
|
|
7'h1e: xt_code <= 7'h03;
|
| 408 |
|
|
7'h1f: xt_code <= 7'h5b;
|
| 409 |
|
|
7'h20: xt_code <= 7'h67;
|
| 410 |
|
|
7'h21: xt_code <= 7'h2e;
|
| 411 |
|
|
7'h22: xt_code <= 7'h2d;
|
| 412 |
|
|
7'h23: xt_code <= 7'h20;
|
| 413 |
|
|
7'h24: xt_code <= 7'h12;
|
| 414 |
|
|
7'h25: xt_code <= 7'h05;
|
| 415 |
|
|
7'h26: xt_code <= 7'h04;
|
| 416 |
|
|
7'h27: xt_code <= 7'h5c;
|
| 417 |
|
|
7'h28: xt_code <= 7'h68;
|
| 418 |
|
|
7'h29: xt_code <= 7'h39;
|
| 419 |
|
|
7'h2a: xt_code <= 7'h2f;
|
| 420 |
|
|
7'h2b: xt_code <= 7'h21;
|
| 421 |
|
|
7'h2c: xt_code <= 7'h14;
|
| 422 |
|
|
7'h2d: xt_code <= 7'h13;
|
| 423 |
|
|
7'h2e: xt_code <= 7'h06;
|
| 424 |
|
|
7'h2f: xt_code <= 7'h5d;
|
| 425 |
|
|
7'h30: xt_code <= 7'h69;
|
| 426 |
|
|
7'h31: xt_code <= 7'h31;
|
| 427 |
|
|
7'h32: xt_code <= 7'h30;
|
| 428 |
|
|
7'h33: xt_code <= 7'h23;
|
| 429 |
|
|
7'h34: xt_code <= 7'h22;
|
| 430 |
|
|
7'h35: xt_code <= 7'h15;
|
| 431 |
|
|
7'h36: xt_code <= 7'h07;
|
| 432 |
|
|
7'h37: xt_code <= 7'h5e;
|
| 433 |
|
|
7'h38: xt_code <= 7'h6a;
|
| 434 |
|
|
7'h39: xt_code <= 7'h72;
|
| 435 |
|
|
7'h3a: xt_code <= 7'h32;
|
| 436 |
|
|
7'h3b: xt_code <= 7'h24;
|
| 437 |
|
|
7'h3c: xt_code <= 7'h16;
|
| 438 |
|
|
7'h3d: xt_code <= 7'h08;
|
| 439 |
|
|
7'h3e: xt_code <= 7'h09;
|
| 440 |
|
|
7'h3f: xt_code <= 7'h5f;
|
| 441 |
|
|
7'h40: xt_code <= 7'h6b;
|
| 442 |
|
|
7'h41: xt_code <= 7'h33;
|
| 443 |
|
|
7'h42: xt_code <= 7'h25;
|
| 444 |
|
|
7'h43: xt_code <= 7'h17;
|
| 445 |
|
|
7'h44: xt_code <= 7'h18;
|
| 446 |
|
|
7'h45: xt_code <= 7'h0b;
|
| 447 |
|
|
7'h46: xt_code <= 7'h0a;
|
| 448 |
|
|
7'h47: xt_code <= 7'h60;
|
| 449 |
|
|
7'h48: xt_code <= 7'h6c;
|
| 450 |
|
|
7'h49: xt_code <= 7'h34;
|
| 451 |
|
|
7'h4a: xt_code <= 7'h35;
|
| 452 |
|
|
7'h4b: xt_code <= 7'h26;
|
| 453 |
|
|
7'h4c: xt_code <= 7'h27;
|
| 454 |
|
|
7'h4d: xt_code <= 7'h19;
|
| 455 |
|
|
7'h4e: xt_code <= 7'h0c;
|
| 456 |
|
|
7'h4f: xt_code <= 7'h61;
|
| 457 |
|
|
7'h50: xt_code <= 7'h6d;
|
| 458 |
|
|
7'h51: xt_code <= 7'h73;
|
| 459 |
|
|
7'h52: xt_code <= 7'h28;
|
| 460 |
|
|
7'h53: xt_code <= 7'h74;
|
| 461 |
|
|
7'h54: xt_code <= 7'h1a;
|
| 462 |
|
|
7'h55: xt_code <= 7'h0d;
|
| 463 |
|
|
7'h56: xt_code <= 7'h62;
|
| 464 |
|
|
7'h57: xt_code <= 7'h6e;
|
| 465 |
|
|
7'h58: xt_code <= 7'h3a;
|
| 466 |
|
|
7'h59: xt_code <= 7'h36;
|
| 467 |
|
|
7'h5a: xt_code <= 7'h1c;
|
| 468 |
|
|
7'h5b: xt_code <= 7'h1b;
|
| 469 |
|
|
7'h5c: xt_code <= 7'h75;
|
| 470 |
|
|
7'h5d: xt_code <= 7'h2b;
|
| 471 |
|
|
7'h5e: xt_code <= 7'h63;
|
| 472 |
|
|
7'h5f: xt_code <= 7'h76;
|
| 473 |
|
|
7'h60: xt_code <= 7'h55;
|
| 474 |
|
|
7'h61: xt_code <= 7'h56;
|
| 475 |
|
|
7'h62: xt_code <= 7'h77;
|
| 476 |
|
|
7'h63: xt_code <= 7'h78;
|
| 477 |
|
|
7'h64: xt_code <= 7'h79;
|
| 478 |
|
|
7'h65: xt_code <= 7'h7a;
|
| 479 |
|
|
7'h66: xt_code <= 7'h0e;
|
| 480 |
|
|
7'h67: xt_code <= 7'h7b;
|
| 481 |
|
|
7'h68: xt_code <= 7'h7c;
|
| 482 |
|
|
7'h69: xt_code <= 7'h4f;
|
| 483 |
|
|
7'h6a: xt_code <= 7'h7d;
|
| 484 |
|
|
7'h6b: xt_code <= 7'h4b;
|
| 485 |
|
|
7'h6c: xt_code <= 7'h47;
|
| 486 |
|
|
7'h6d: xt_code <= 7'h7e;
|
| 487 |
|
|
7'h6e: xt_code <= 7'h7f;
|
| 488 |
|
|
7'h6f: xt_code <= 7'h6f;
|
| 489 |
|
|
7'h70: xt_code <= 7'h52;
|
| 490 |
|
|
7'h71: xt_code <= 7'h53;
|
| 491 |
|
|
7'h72: xt_code <= 7'h50;
|
| 492 |
|
|
7'h73: xt_code <= 7'h4c;
|
| 493 |
|
|
7'h74: xt_code <= 7'h4d;
|
| 494 |
|
|
7'h75: xt_code <= 7'h48;
|
| 495 |
|
|
7'h76: xt_code <= 7'h01;
|
| 496 |
|
|
7'h77: xt_code <= 7'h45;
|
| 497 |
|
|
7'h78: xt_code <= 7'h57;
|
| 498 |
|
|
7'h79: xt_code <= 7'h4e;
|
| 499 |
|
|
7'h7a: xt_code <= 7'h51;
|
| 500 |
|
|
7'h7b: xt_code <= 7'h4a;
|
| 501 |
|
|
7'h7c: xt_code <= 7'h37;
|
| 502 |
|
|
7'h7d: xt_code <= 7'h49;
|
| 503 |
|
|
7'h7e: xt_code <= 7'h46;
|
| 504 |
|
|
7'h7f: xt_code <= 7'h54;
|
| 505 |
|
|
endcase
|
| 506 |
|
|
endmodule
|
