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[/] [zet86/] [trunk/] [soc/] [vga/] [rtl/] [ram2k_b16_attr.v] - Blame information for rev 49

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Line No. Rev Author Line
1 40 zeus 
/*
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 *  Copyright (c) 2008  Zeus Gomez Marmolejo <zeus@opencores.org>
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 *
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 *  This file is part of the Zet processor. This processor is free
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 *  hardware; you can redistribute it and/or modify it under the terms of
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 *  the GNU General Public License as published by the Free Software
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 *  Foundation; either version 3, or (at your option) any later version.
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 *
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 *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
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 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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 *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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 *  License for more details.
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 *
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 *  You should have received a copy of the GNU General Public License
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 *  along with Zet; see the file COPYING. If not, see
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 *  <http://www.gnu.org/licenses/>.
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 */
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19 39 zeus 
`timescale 1ns/10ps
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module ram_2k_attr (clk, rst, cs, we, addr, rdata, wdata);
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  // IO Ports
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  input clk;
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  input rst;
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  input cs;
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  input we;
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  input [10:0] addr;
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  output [7:0] rdata;
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  input [7:0] wdata;
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  // Net declarations
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  wire dp;
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  // Module instantiations
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  RAMB16_S9 ram (.DO(rdata),
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                 .DOP (dp),
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                 .ADDR (addr),
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                 .CLK (clk),
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                 .DI (wdata),
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                 .DIP (dp),
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                 .EN (cs),
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                 .SSR (rst),
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                 .WE (we));
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    defparam ram.INIT_00 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_01 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_02 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_03 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_04 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_05 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_06 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_07 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_08 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_09 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_0A = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_0B = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_0C = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_0D = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_0E = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_0F = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_10 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_11 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_12 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_13 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_14 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_15 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_16 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_17 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_18 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_19 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_1A = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_1B = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_1C = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_1D = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_1E = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_1F = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_20 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_21 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_22 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_23 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_24 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_25 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_26 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_27 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_28 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_29 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_2A = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_2B = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_2C = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_2D = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_2E = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_2F = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_30 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_31 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_32 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_33 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_34 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_35 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_36 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_37 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_38 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_39 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_3A = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_3B = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_3C = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_3D = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_3E = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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    defparam ram.INIT_3F = 256'h0707070707070707070707070707070707070707070707070707070707070707;
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endmodule

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