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[/] [zet86/] [trunk/] [soc/] [vga/] [sim/] [tb.do] - Blame information for rev 49

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#vdel -all -lib work
vmap unisims /opt/Xilinx/10.1/modelsim/verilog/unisims
vlib work
vlog -work work -lint ../rtl/vdu.v vdu_tb.v ../rtl/ram2k_b16_attr.v ../rtl/ram2k_b16.v ../rtl/char_rom_b16.v
vlog -work work /opt/Xilinx/10.1/ISE/verilog/src/glbl.v
vsim -L /opt/Xilinx/10.1/modelsim/verilog/unisims -novopt -t ns work.vdu_tb work.glbl
add wave -radix hexadecimal /vdu_tb/vdu0/*

Line No.	Rev	Author	Line
1	40	zeus	`#vdel -all -lib work`
2	39	zeus	`vmap unisims /opt/Xilinx/10.1/modelsim/verilog/unisims`
3			`vlib work`
4	40	zeus	`vlog -work work -lint ../rtl/vdu.v vdu_tb.v ../rtl/ram2k_b16_attr.v ../rtl/ram2k_b16.v ../rtl/char_rom_b16.v`
5	39	zeus	`vlog -work work /opt/Xilinx/10.1/ISE/verilog/src/glbl.v`
6			`vsim -L /opt/Xilinx/10.1/modelsim/verilog/unisims -novopt -t ns work.vdu_tb work.glbl`
7			`add wave -radix hexadecimal /vdu_tb/vdu0/*`

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[/] [zet86/] [trunk/] [soc/] [vga/] [sim/] [tb.do] - Blame information for rev 49