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[/] [zet86/] [trunk/] [src/] [bochs-diff-2.3.7/] [disasm/] [syntax.cc] - Blame information for rev 49

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Line No. Rev Author Line
1 39 zeus
/////////////////////////////////////////////////////////////////////////
2 43 zeus
// $Id: syntax.cc,v 1.5 2009-02-06 03:48:30 zeus Exp $
3 39 zeus
/////////////////////////////////////////////////////////////////////////
4
 
5
#include <stdio.h>
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#include "disasm.h"
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//////////////////
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// Intel STYLE
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//////////////////
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#define BX_DISASM_SUPPORT_X86_64
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#ifdef BX_DISASM_SUPPORT_X86_64
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static const char *intel_general_16bit_regname[16] = {
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    "ax",  "cx",  "dx",   "bx",   "sp",   "bp",   "si",   "di",
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    "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
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};
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static const char *intel_general_32bit_regname[16] = {
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    "eax", "ecx", "edx",  "ebx",  "esp",  "ebp",  "esi",  "edi",
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    "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
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};
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static const char *intel_general_64bit_regname[16] = {
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    "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
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    "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15"
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};
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static const char *intel_general_8bit_regname_rex[16] = {
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    "al",  "cl",  "dl",   "bl",   "spl",  "bpl",  "sil",  "dil",
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    "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
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};
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#else
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static const char *intel_general_16bit_regname[8] = {
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    "ax",  "cx",  "dx",  "bx",  "sp",  "bp",  "si",  "di"
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};
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static const char *intel_general_32bit_regname[8] = {
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    "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi"
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};
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#endif
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static const char *intel_general_8bit_regname[8] = {
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    "al",  "cl",  "dl",  "bl",  "ah",  "ch",  "dh",  "bh"
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};
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static const char *intel_segment_name[8] = {
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    "es",  "cs",  "ss",  "ds",  "fs",  "gs",  "??",  "??"
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};
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static const char *intel_index16[8] = {
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    "bx+si",
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    "bx+di",
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    "bp+si",
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    "bp+di",
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    "si",
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    "di",
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    "bp",
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    "bx"
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};
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//////////////////
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// AT&T STYLE
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//////////////////
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#ifdef BX_DISASM_SUPPORT_X86_64
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static const char *att_general_16bit_regname[16] = {
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    "%ax",  "%cx",  "%dx",   "%bx",   "%sp",   "%bp",   "%si",   "%di",
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    "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
77
};
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static const char *att_general_32bit_regname[16] = {
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    "%eax", "%ecx", "%edx",  "%ebx",  "%esp",  "%ebp",  "%esi",  "%edi",
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    "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
82
};
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static const char *att_general_64bit_regname[16] = {
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    "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
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    "%r8",  "%r9",  "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
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};
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static const char *att_general_8bit_regname_rex[16] = {
90
    "%al",  "%cl",  "%dl",   "%bl",   "%spl",  "%bpl",  "%sil",  "%dil",
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    "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
92
};
93
 
94
#else
95
 
96
static const char *att_general_16bit_regname[8] = {
97
    "%ax",  "%cx",  "%dx",  "%bx",  "%sp",  "%bp",  "%si",  "%di"
98
};
99
 
100
static const char *att_general_32bit_regname[8] = {
101
    "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi"
102
};
103
 
104
#endif
105
 
106
static const char *att_general_8bit_regname[8] = {
107
    "%al",  "%cl",  "%dl",  "%bl",  "%ah",  "%ch",  "%dh",  "%bh"
108
};
109
 
110
static const char *att_segment_name[8] = {
111
    "%es",  "%cs",  "%ss",  "%ds",  "%fs",  "%gs",  "%??",  "%??"
112
};
113
 
114
static const char *att_index16[8] = {
115
    "%bx,%si",
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    "%bx,%di",
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    "%bp,%si",
118
    "%bp,%di",
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    "%si",
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    "%di",
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    "%bp",
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    "%bx"
123
};
124
 
125
#define NULL_SEGMENT_REGISTER 7
126
 
127
void disassembler::initialize_modrm_segregs()
128
{
129
  sreg_mod00_rm16[0] = segment_name[DS_REG];
130
  sreg_mod00_rm16[1] = segment_name[DS_REG];
131
  sreg_mod00_rm16[2] = segment_name[SS_REG];
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  sreg_mod00_rm16[3] = segment_name[SS_REG];
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  sreg_mod00_rm16[4] = segment_name[DS_REG];
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  sreg_mod00_rm16[5] = segment_name[DS_REG];
135
  sreg_mod00_rm16[6] = segment_name[DS_REG];
136
  sreg_mod00_rm16[7] = segment_name[DS_REG];
137
 
138
  sreg_mod01or10_rm16[0] = segment_name[DS_REG];
139
  sreg_mod01or10_rm16[1] = segment_name[DS_REG];
140
  sreg_mod01or10_rm16[2] = segment_name[SS_REG];
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  sreg_mod01or10_rm16[3] = segment_name[SS_REG];
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  sreg_mod01or10_rm16[4] = segment_name[DS_REG];
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  sreg_mod01or10_rm16[5] = segment_name[DS_REG];
144
  sreg_mod01or10_rm16[6] = segment_name[SS_REG];
145
  sreg_mod01or10_rm16[7] = segment_name[DS_REG];
146
 
147
  sreg_mod01or10_rm32[0]  = segment_name[DS_REG];
148
  sreg_mod01or10_rm32[1]  = segment_name[DS_REG];
149
  sreg_mod01or10_rm32[2]  = segment_name[DS_REG];
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  sreg_mod01or10_rm32[3]  = segment_name[DS_REG];
151
  sreg_mod01or10_rm32[4]  = segment_name[NULL_SEGMENT_REGISTER];
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  sreg_mod01or10_rm32[5]  = segment_name[SS_REG];
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  sreg_mod01or10_rm32[6]  = segment_name[DS_REG];
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  sreg_mod01or10_rm32[7]  = segment_name[DS_REG];
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  sreg_mod01or10_rm32[8]  = segment_name[DS_REG];
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  sreg_mod01or10_rm32[9]  = segment_name[DS_REG];
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  sreg_mod01or10_rm32[10] = segment_name[DS_REG];
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  sreg_mod01or10_rm32[11] = segment_name[DS_REG];
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  sreg_mod01or10_rm32[12] = segment_name[NULL_SEGMENT_REGISTER];
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  sreg_mod01or10_rm32[13] = segment_name[DS_REG];
161
  sreg_mod01or10_rm32[14] = segment_name[DS_REG];
162
  sreg_mod01or10_rm32[15] = segment_name[DS_REG];
163
 
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  sreg_mod00_base32[0]  = segment_name[DS_REG];
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  sreg_mod00_base32[1]  = segment_name[DS_REG];
166
  sreg_mod00_base32[2]  = segment_name[DS_REG];
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  sreg_mod00_base32[3]  = segment_name[DS_REG];
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  sreg_mod00_base32[4]  = segment_name[SS_REG];
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  sreg_mod00_base32[5]  = segment_name[DS_REG];
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  sreg_mod00_base32[6]  = segment_name[DS_REG];
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  sreg_mod00_base32[7]  = segment_name[DS_REG];
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  sreg_mod00_base32[8]  = segment_name[DS_REG];
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  sreg_mod00_base32[9]  = segment_name[DS_REG];
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  sreg_mod00_base32[10] = segment_name[DS_REG];
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  sreg_mod00_base32[11] = segment_name[DS_REG];
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  sreg_mod00_base32[12] = segment_name[DS_REG];
177
  sreg_mod00_base32[13] = segment_name[DS_REG];
178
  sreg_mod00_base32[14] = segment_name[DS_REG];
179
  sreg_mod00_base32[15] = segment_name[DS_REG];
180
 
181
  sreg_mod01or10_base32[0]  = segment_name[DS_REG];
182
  sreg_mod01or10_base32[1]  = segment_name[DS_REG];
183
  sreg_mod01or10_base32[2]  = segment_name[DS_REG];
184
  sreg_mod01or10_base32[3]  = segment_name[DS_REG];
185
  sreg_mod01or10_base32[4]  = segment_name[SS_REG];
186
  sreg_mod01or10_base32[5]  = segment_name[SS_REG];
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  sreg_mod01or10_base32[6]  = segment_name[DS_REG];
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  sreg_mod01or10_base32[7]  = segment_name[DS_REG];
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  sreg_mod01or10_base32[8]  = segment_name[DS_REG];
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  sreg_mod01or10_base32[9]  = segment_name[DS_REG];
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  sreg_mod01or10_base32[10] = segment_name[DS_REG];
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  sreg_mod01or10_base32[11] = segment_name[DS_REG];
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  sreg_mod01or10_base32[12] = segment_name[DS_REG];
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  sreg_mod01or10_base32[13] = segment_name[DS_REG];
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  sreg_mod01or10_base32[14] = segment_name[DS_REG];
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  sreg_mod01or10_base32[15] = segment_name[DS_REG];
197
}
198
 
199
//////////////////
200
// Intel STYLE
201
//////////////////
202
 
203
void disassembler::set_syntax_intel()
204
{
205
  intel_mode = 1;
206
 
207
  general_16bit_regname = intel_general_16bit_regname;
208
  general_8bit_regname = intel_general_8bit_regname;
209
  general_32bit_regname = intel_general_32bit_regname;
210
  general_8bit_regname_rex = intel_general_8bit_regname_rex;
211
  general_64bit_regname = intel_general_64bit_regname;
212
 
213
  segment_name = intel_segment_name;
214
  index16 = intel_index16;
215
 
216
  initialize_modrm_segregs();
217
}
218
 
219
void disassembler::print_disassembly_intel(const x86_insn *insn, const BxDisasmOpcodeInfo_t *entry)
220
{
221
  // print opcode
222
  dis_sprintf("%s ", entry->IntelOpcode);
223
 
224
  if (entry->Operand1) {
225
    (this->*entry->Operand1)(insn);
226
  }
227
  if (entry->Operand2) {
228
    dis_sprintf(", ");
229
    (this->*entry->Operand2)(insn);
230
  }
231
  if (entry->Operand3) {
232
    dis_sprintf(", ");
233
    (this->*entry->Operand3)(insn);
234
  }
235
  if (entry->Operand4) {
236
    dis_sprintf(", ");
237
    (this->*entry->Operand4)(insn);
238
  }
239
}
240
 
241
//////////////////
242
// AT&T STYLE
243
//////////////////
244
 
245
void disassembler::set_syntax_att()
246
{
247
  intel_mode = 0;
248
 
249
  general_16bit_regname = att_general_16bit_regname;
250
  general_8bit_regname = att_general_8bit_regname;
251
  general_32bit_regname = att_general_32bit_regname;
252
  general_8bit_regname_rex = att_general_8bit_regname_rex;
253
  general_64bit_regname = att_general_64bit_regname;
254
 
255
  segment_name = att_segment_name;
256
  index16 = att_index16;
257
 
258
  initialize_modrm_segregs();
259
}
260
 
261
void disassembler::toggle_syntax_mode()
262
{
263
  if (intel_mode) set_syntax_att();
264
  else set_syntax_intel();
265
}
266
/*
267
void disassembler::print_disassembly_att(const x86_insn *insn, const BxDisasmOpcodeInfo_t *entry)
268
{
269
  // print opcode
270
  dis_sprintf("%s ", entry->AttOpcode);
271
 
272
  if (entry->Operand4) {
273
    (this->*entry->Operand4)(insn);
274
    dis_sprintf(", ");
275
  }
276
  if (entry->Operand3) {
277
    (this->*entry->Operand3)(insn);
278
    dis_sprintf(", ");
279
  }
280
  if (entry->Operand2) {
281
    (this->*entry->Operand2)(insn);
282
    dis_sprintf(", ");
283
  }
284
  if (entry->Operand1) {
285
    (this->*entry->Operand1)(insn);
286
  }
287
}
288
*/
289
void disassembler::print_disassembly_att(const x86_insn *insn, const BxDisasmOpcodeInfo_t *entry)
290
{
291
  // print opcode
292
  dis_sprintf("%s", entry->AttOpcode);
293
}

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