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[/] [zet86/] [trunk/] [src/] [bochs-diff-2.3.7/] [instrument/] [zet/] [instrument.cc] - Blame information for rev 43

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1 39 zeus
/////////////////////////////////////////////////////////////////////////
2 43 zeus
// $Id: instrument.cc,v 1.5 2009-02-06 03:48:31 zeus Exp $
3 39 zeus
/////////////////////////////////////////////////////////////////////////
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//
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//  Copyright (C) 2001  MandrakeSoft S.A.
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//
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//    MandrakeSoft S.A.
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//    43, rue d'Aboukir
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//    75002 Paris - France
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//    http://www.linux-mandrake.com/
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//    http://www.mandrakesoft.com/
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//
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//  This library is free software; you can redistribute it and/or
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//  modify it under the terms of the GNU Lesser General Public
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//  License as published by the Free Software Foundation; either
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//  version 2 of the License, or (at your option) any later version.
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//
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//  This library is distributed in the hope that it will be useful,
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//  but WITHOUT ANY WARRANTY; without even the implied warranty of
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//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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//  Lesser General Public License for more details.
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//
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//  You should have received a copy of the GNU Lesser General Public
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//  License along with this library; if not, write to the Free Software
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//  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
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#include <assert.h>
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#include <map>
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#include <string>
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#include <iostream>
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using std::cerr;
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using std::endl;
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#include "bochs.h"
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#include "cpu/cpu.h"
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// maximum size of an instruction
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#define MAX_OPCODE_SIZE 16
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// maximum physical addresses an instruction can generate
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#define MAX_DATA_ACCESSES 1024
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// Use this variable to turn on/off collection of instrumentation data
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// If you are not using the debugger to turn this on/off, then possibly
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// start this at 1 instead of 0.
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typedef std::map<std::string, unsigned> TStrUIntMap;
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TStrUIntMap *stats = 0;
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unsigned long ninstr = 0;
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static disassembler bx_disassembler;
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static struct instruction_t {
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  bx_bool  valid;        // is current instruction valid
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  unsigned opcode_size;
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  unsigned nprefixes;
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  Bit8u    opcode[MAX_OPCODE_SIZE];
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  bx_bool  is32, is64;
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  unsigned num_data_accesses;
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  struct {
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    bx_address laddr;     // linear address
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    bx_phy_address paddr; // physical address
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    unsigned op;          // BX_READ, BX_WRITE or BX_RW
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    unsigned size;        // 1 .. 8
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  } data_access[MAX_DATA_ACCESSES];
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  bx_bool is_branch;
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  bx_bool is_taken;
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  bx_address target_linear;
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} *instruction;
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static logfunctions *instrument_log = new logfunctions ();
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#define LOG_THIS instrument_log->
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void bx_instr_init(unsigned cpu)
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{
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  assert(cpu < BX_SMP_PROCESSORS);
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  if (instruction == NULL)
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      instruction = new struct instruction_t[BX_SMP_PROCESSORS];
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  fprintf(stderr, "Initialize cpu %d\n", cpu);
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  bx_disassembler.toggle_syntax_mode();
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}
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void bx_instr_reset(unsigned cpu)
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{
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  instruction[cpu].valid = 0;
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  instruction[cpu].nprefixes = 0;
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  instruction[cpu].num_data_accesses = 0;
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  instruction[cpu].is_branch = 0;
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}
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void bx_instr_print()
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{
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   if (stats)
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     {
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       cerr << "stats contains:\nKey\tValue\n";
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       // use const_iterator to walk through elements of pairs
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       for ( std::map<std::string, unsigned>
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              ::const_iterator iter = stats->begin();
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             iter != stats->end(); ++iter )
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         cerr << iter->first << '\t' << iter->second << '\n';
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       cerr << endl;
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       cerr << "# instr: " << ninstr << endl;
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     }
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   else
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     {
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       cerr << "There's no statistics to show!" << endl;
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     }
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}
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void bx_instr_start()
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{
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  if (stats) cerr << "instrumentation already started" << endl;
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  else stats = new TStrUIntMap;
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}
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void bx_instr_stop()
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{
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  if (stats)
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    {
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      delete stats;
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      stats = 0;
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    }
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  else
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    {
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      cerr << "there's no statistics to stop!" << endl;
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    }
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}
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void bx_instr_new_instruction(unsigned cpu)
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{
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  Bit16u sel;
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  if (!stats) return;
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  ninstr++;
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  instruction_t *i = &instruction[cpu];
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  if (i->valid)
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  {
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    char disasm_tbuf[512];      // buffer for instruction disassembly
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    unsigned length = i->opcode_size, n;
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    bx_disassembler.disasm(i->is32, i->is64, 0, 0, i->opcode, disasm_tbuf);
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    if(length != 0)
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    {
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      sel = bx_cpu.sregs[BX_SEG_REG_CS].selector.value;
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      if (sel!=0xf000 && sel!=0xc000) {
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        (*stats)[std::string(disasm_tbuf)]++;
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      }
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    }
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  }
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  instruction[cpu].valid = 0;
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  instruction[cpu].nprefixes = 0;
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  instruction[cpu].num_data_accesses = 0;
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  instruction[cpu].is_branch = 0;
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}
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static void branch_taken(unsigned cpu, bx_address new_eip)
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{
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  if (!stats || !instruction[cpu].valid) return;
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  // find linear address
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  bx_address laddr = BX_CPU(cpu)->get_laddr(BX_SEG_REG_CS, new_eip);
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  instruction[cpu].is_branch = 1;
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  instruction[cpu].is_taken = 1;
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  instruction[cpu].target_linear = laddr;
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}
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void bx_instr_cnear_branch_taken(unsigned cpu, bx_address new_eip)
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{
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  branch_taken(cpu, new_eip);
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}
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void bx_instr_cnear_branch_not_taken(unsigned cpu)
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{
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  if (!stats || !instruction[cpu].valid) return;
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  instruction[cpu].is_branch = 1;
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  instruction[cpu].is_taken = 0;
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}
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void bx_instr_ucnear_branch(unsigned cpu, unsigned what, bx_address new_eip)
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{
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  branch_taken(cpu, new_eip);
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}
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void bx_instr_far_branch(unsigned cpu, unsigned what, Bit16u new_cs, bx_address new_eip)
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{
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  branch_taken(cpu, new_eip);
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}
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void bx_instr_opcode(unsigned cpu, const Bit8u *opcode, unsigned len, bx_bool is32, bx_bool is64)
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{
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  if (!stats) return;
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  for(unsigned i=0;i<len;i++)
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  {
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    instruction[cpu].opcode[i] = opcode[i];
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  }
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  instruction[cpu].is32 = is32;
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  instruction[cpu].is64 = is64;
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  instruction[cpu].opcode_size = len;
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}
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void bx_instr_fetch_decode_completed(unsigned cpu, bxInstruction_c *i)
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{
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  if(stats) instruction[cpu].valid = 1;
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}
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void bx_instr_prefix(unsigned cpu, Bit8u prefix)
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{
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  if(stats) instruction[cpu].nprefixes++;
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}
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void bx_instr_interrupt(unsigned cpu, unsigned vector)
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{
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  char tmpbuf[50];
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  Bit16u sel;
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  if(stats)
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  {
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    sel = bx_cpu.sregs[BX_SEG_REG_CS].selector.value;
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    if (sel!=0xf000 && sel!=0xc000) {
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      sprintf(tmpbuf, "int %02xh AH=%02x", vector,
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        bx_cpu.gen_reg[0].word.byte.rh);
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      (*stats)[std::string(tmpbuf)]++;
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    }
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  }
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}
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void bx_instr_exception(unsigned cpu, unsigned vector)
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{
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  char tmpbuf[50];
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  if(stats)
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  {
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    sprintf(tmpbuf, "exc %02xh", vector);
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    (*stats)[std::string(tmpbuf)]++;
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  }
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}
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void bx_instr_hwinterrupt(unsigned cpu, unsigned vector, Bit16u cs, bx_address eip)
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{
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  char tmpbuf[50];
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  if(stats)
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  {
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    sprintf(tmpbuf, "hwint %02xh", vector);
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    (*stats)[std::string(tmpbuf)]++;
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  }
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}
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void bx_instr_mem_data(unsigned cpu, unsigned seg, bx_address offset, unsigned len, unsigned rw)
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{
263
  unsigned index;
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  bx_phy_address phy;
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  if(!stats || !instruction[cpu].valid) return;
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268
  if (instruction[cpu].num_data_accesses >= MAX_DATA_ACCESSES)
269
  {
270
    return;
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  }
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273
  bx_address lin = BX_CPU(cpu)->get_laddr(seg, offset);
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  bx_bool page_valid = BX_CPU(cpu)->dbg_xlate_linear2phy(lin, &phy);
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  phy = A20ADDR(phy);
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  // If linear translation doesn't exist, a paging exception will occur.
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  // Invalidate physical address data for now.
279
  if (!page_valid)
280
  {
281
    phy = 0;
282
  }
283
 
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  index = instruction[cpu].num_data_accesses;
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  instruction[cpu].data_access[index].laddr = lin;
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  instruction[cpu].data_access[index].paddr = phy;
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  instruction[cpu].data_access[index].op    = rw;
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//  instruction[cpu].data_access[index].size  = size;
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  instruction[cpu].num_data_accesses++;
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}
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void bx_instr_mem_data_access(unsigned cpu, unsigned seg, unsigned offset, unsigned len, unsigned rw)
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{
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  return;
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}

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