OpenCores
URL https://opencores.org/ocsvn/zet86/zet86/trunk

Subversion Repositories zet86

[/] [zet86/] [trunk/] [src/] [bochs-diff-2.3.7/] [instrument/] [zet/] [instrument.cc] - Blame information for rev 49

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 39 zeus
/////////////////////////////////////////////////////////////////////////
2 43 zeus
// $Id: instrument.cc,v 1.5 2009-02-06 03:48:31 zeus Exp $
3 39 zeus
/////////////////////////////////////////////////////////////////////////
4
//
5
//  Copyright (C) 2001  MandrakeSoft S.A.
6
//
7
//    MandrakeSoft S.A.
8
//    43, rue d'Aboukir
9
//    75002 Paris - France
10
//    http://www.linux-mandrake.com/
11
//    http://www.mandrakesoft.com/
12
//
13
//  This library is free software; you can redistribute it and/or
14
//  modify it under the terms of the GNU Lesser General Public
15
//  License as published by the Free Software Foundation; either
16
//  version 2 of the License, or (at your option) any later version.
17
//
18
//  This library is distributed in the hope that it will be useful,
19
//  but WITHOUT ANY WARRANTY; without even the implied warranty of
20
//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
21
//  Lesser General Public License for more details.
22
//
23
//  You should have received a copy of the GNU Lesser General Public
24
//  License along with this library; if not, write to the Free Software
25
//  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
26
 
27
 
28
#include <assert.h>
29
#include <map>
30
#include <string>
31
#include <iostream>
32
using std::cerr;
33
using std::endl;
34
 
35
 
36
#include "bochs.h"
37
#include "cpu/cpu.h"
38
 
39
// maximum size of an instruction
40
#define MAX_OPCODE_SIZE 16
41
 
42
// maximum physical addresses an instruction can generate
43
#define MAX_DATA_ACCESSES 1024
44
 
45
// Use this variable to turn on/off collection of instrumentation data
46
// If you are not using the debugger to turn this on/off, then possibly
47
// start this at 1 instead of 0.
48
typedef std::map<std::string, unsigned> TStrUIntMap;
49
TStrUIntMap *stats = 0;
50
 
51
unsigned long ninstr = 0;
52
 
53
static disassembler bx_disassembler;
54
 
55
static struct instruction_t {
56
  bx_bool  valid;        // is current instruction valid
57
  unsigned opcode_size;
58
  unsigned nprefixes;
59
  Bit8u    opcode[MAX_OPCODE_SIZE];
60
  bx_bool  is32, is64;
61
  unsigned num_data_accesses;
62
  struct {
63
    bx_address laddr;     // linear address
64
    bx_phy_address paddr; // physical address
65
    unsigned op;          // BX_READ, BX_WRITE or BX_RW
66
    unsigned size;        // 1 .. 8
67
  } data_access[MAX_DATA_ACCESSES];
68
  bx_bool is_branch;
69
  bx_bool is_taken;
70
  bx_address target_linear;
71
} *instruction;
72
 
73
static logfunctions *instrument_log = new logfunctions ();
74
#define LOG_THIS instrument_log->
75
 
76
void bx_instr_init(unsigned cpu)
77
{
78
  assert(cpu < BX_SMP_PROCESSORS);
79
 
80
  if (instruction == NULL)
81
      instruction = new struct instruction_t[BX_SMP_PROCESSORS];
82
 
83
  fprintf(stderr, "Initialize cpu %d\n", cpu);
84
 
85
  bx_disassembler.toggle_syntax_mode();
86
}
87
 
88
void bx_instr_reset(unsigned cpu)
89
{
90
  instruction[cpu].valid = 0;
91
  instruction[cpu].nprefixes = 0;
92
  instruction[cpu].num_data_accesses = 0;
93
  instruction[cpu].is_branch = 0;
94
}
95
 
96
void bx_instr_print()
97
{
98
   if (stats)
99
     {
100
       cerr << "stats contains:\nKey\tValue\n";
101
 
102
       // use const_iterator to walk through elements of pairs
103
       for ( std::map<std::string, unsigned>
104
              ::const_iterator iter = stats->begin();
105
             iter != stats->end(); ++iter )
106
 
107
         cerr << iter->first << '\t' << iter->second << '\n';
108
 
109
       cerr << endl;
110
       cerr << "# instr: " << ninstr << endl;
111
     }
112
   else
113
     {
114
       cerr << "There's no statistics to show!" << endl;
115
     }
116
}
117
 
118
void bx_instr_start()
119
{
120
  if (stats) cerr << "instrumentation already started" << endl;
121
  else stats = new TStrUIntMap;
122
}
123
 
124
void bx_instr_stop()
125
{
126
  if (stats)
127
    {
128
      delete stats;
129
      stats = 0;
130
    }
131
  else
132
    {
133
      cerr << "there's no statistics to stop!" << endl;
134
    }
135
}
136
 
137
void bx_instr_new_instruction(unsigned cpu)
138
{
139
  Bit16u sel;
140
  if (!stats) return;
141
 
142
  ninstr++;
143
  instruction_t *i = &instruction[cpu];
144
 
145
  if (i->valid)
146
  {
147
    char disasm_tbuf[512];      // buffer for instruction disassembly
148
    unsigned length = i->opcode_size, n;
149
 
150
    bx_disassembler.disasm(i->is32, i->is64, 0, 0, i->opcode, disasm_tbuf);
151
 
152
    if(length != 0)
153
    {
154
      sel = bx_cpu.sregs[BX_SEG_REG_CS].selector.value;
155
      if (sel!=0xf000 && sel!=0xc000) {
156
        (*stats)[std::string(disasm_tbuf)]++;
157
      }
158
    }
159
  }
160
 
161
  instruction[cpu].valid = 0;
162
  instruction[cpu].nprefixes = 0;
163
  instruction[cpu].num_data_accesses = 0;
164
  instruction[cpu].is_branch = 0;
165
}
166
 
167
static void branch_taken(unsigned cpu, bx_address new_eip)
168
{
169
  if (!stats || !instruction[cpu].valid) return;
170
 
171
  // find linear address
172
  bx_address laddr = BX_CPU(cpu)->get_laddr(BX_SEG_REG_CS, new_eip);
173
 
174
  instruction[cpu].is_branch = 1;
175
  instruction[cpu].is_taken = 1;
176
  instruction[cpu].target_linear = laddr;
177
}
178
 
179
void bx_instr_cnear_branch_taken(unsigned cpu, bx_address new_eip)
180
{
181
  branch_taken(cpu, new_eip);
182
}
183
 
184
void bx_instr_cnear_branch_not_taken(unsigned cpu)
185
{
186
  if (!stats || !instruction[cpu].valid) return;
187
 
188
  instruction[cpu].is_branch = 1;
189
  instruction[cpu].is_taken = 0;
190
}
191
 
192
void bx_instr_ucnear_branch(unsigned cpu, unsigned what, bx_address new_eip)
193
{
194
  branch_taken(cpu, new_eip);
195
}
196
 
197
void bx_instr_far_branch(unsigned cpu, unsigned what, Bit16u new_cs, bx_address new_eip)
198
{
199
  branch_taken(cpu, new_eip);
200
}
201
 
202
void bx_instr_opcode(unsigned cpu, const Bit8u *opcode, unsigned len, bx_bool is32, bx_bool is64)
203
{
204
  if (!stats) return;
205
 
206
  for(unsigned i=0;i<len;i++)
207
  {
208
    instruction[cpu].opcode[i] = opcode[i];
209
  }
210
 
211
  instruction[cpu].is32 = is32;
212
  instruction[cpu].is64 = is64;
213
  instruction[cpu].opcode_size = len;
214
}
215
 
216
void bx_instr_fetch_decode_completed(unsigned cpu, bxInstruction_c *i)
217
{
218
  if(stats) instruction[cpu].valid = 1;
219
}
220
 
221
void bx_instr_prefix(unsigned cpu, Bit8u prefix)
222
{
223
  if(stats) instruction[cpu].nprefixes++;
224
}
225
 
226
void bx_instr_interrupt(unsigned cpu, unsigned vector)
227
{
228
  char tmpbuf[50];
229
  Bit16u sel;
230
  if(stats)
231
  {
232
    sel = bx_cpu.sregs[BX_SEG_REG_CS].selector.value;
233
    if (sel!=0xf000 && sel!=0xc000) {
234
      sprintf(tmpbuf, "int %02xh AH=%02x", vector,
235
        bx_cpu.gen_reg[0].word.byte.rh);
236
      (*stats)[std::string(tmpbuf)]++;
237
    }
238
  }
239
}
240
 
241
void bx_instr_exception(unsigned cpu, unsigned vector)
242
{
243
  char tmpbuf[50];
244
  if(stats)
245
  {
246
    sprintf(tmpbuf, "exc %02xh", vector);
247
    (*stats)[std::string(tmpbuf)]++;
248
  }
249
}
250
 
251
void bx_instr_hwinterrupt(unsigned cpu, unsigned vector, Bit16u cs, bx_address eip)
252
{
253
  char tmpbuf[50];
254
  if(stats)
255
  {
256
    sprintf(tmpbuf, "hwint %02xh", vector);
257
    (*stats)[std::string(tmpbuf)]++;
258
  }
259
}
260
 
261
void bx_instr_mem_data(unsigned cpu, unsigned seg, bx_address offset, unsigned len, unsigned rw)
262
{
263
  unsigned index;
264
  bx_phy_address phy;
265
 
266
  if(!stats || !instruction[cpu].valid) return;
267
 
268
  if (instruction[cpu].num_data_accesses >= MAX_DATA_ACCESSES)
269
  {
270
    return;
271
  }
272
 
273
  bx_address lin = BX_CPU(cpu)->get_laddr(seg, offset);
274
  bx_bool page_valid = BX_CPU(cpu)->dbg_xlate_linear2phy(lin, &phy);
275
  phy = A20ADDR(phy);
276
 
277
  // If linear translation doesn't exist, a paging exception will occur.
278
  // Invalidate physical address data for now.
279
  if (!page_valid)
280
  {
281
    phy = 0;
282
  }
283
 
284
  index = instruction[cpu].num_data_accesses;
285
  instruction[cpu].data_access[index].laddr = lin;
286
  instruction[cpu].data_access[index].paddr = phy;
287
  instruction[cpu].data_access[index].op    = rw;
288
//  instruction[cpu].data_access[index].size  = size;
289
  instruction[cpu].num_data_accesses++;
290
}
291
 
292
void bx_instr_mem_data_access(unsigned cpu, unsigned seg, unsigned offset, unsigned len, unsigned rw)
293
{
294
  return;
295
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.