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/////////////////////////////////////////////////////////////////////////
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// $Id: instrument.h,v 1.1 2008-11-14 03:31:25 zeus Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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// possible types passed to BX_INSTR_TLB_CNTRL()
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#define BX_INSTR_MOV_CR3 10
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#define BX_INSTR_INVLPG 11
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#define BX_INSTR_TASKSWITCH 12
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// possible types passed to BX_INSTR_CACHE_CNTRL()
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#define BX_INSTR_INVD 20
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#define BX_INSTR_WBINVD 21
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// possible types passed to BX_INSTR_FAR_BRANCH()
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#define BX_INSTR_IS_CALL 10
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#define BX_INSTR_IS_RET 11
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#define BX_INSTR_IS_IRET 12
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#define BX_INSTR_IS_JMP 13
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#define BX_INSTR_IS_INT 14
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#define BX_INSTR_IS_SYSCALL 15
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#define BX_INSTR_IS_SYSRET 16
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#define BX_INSTR_IS_SYSENTER 17
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#define BX_INSTR_IS_SYSEXIT 18
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// possible types passed to BX_INSTR_PREFETCH_HINT()
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#define BX_INSTR_PREFETCH_NTA 0
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#define BX_INSTR_PREFETCH_T0 1
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#define BX_INSTR_PREFETCH_T1 2
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#define BX_INSTR_PREFETCH_T2 3
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#if BX_INSTRUMENTATION
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class bxInstruction_c;
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// called from the CPU core
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void bx_instr_init(unsigned cpu);
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void bx_instr_reset(unsigned cpu);
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void bx_instr_start();
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void bx_instr_stop();
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void bx_instr_print();
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void bx_instr_new_instruction(unsigned cpu);
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void bx_instr_cnear_branch_taken(unsigned cpu, bx_address new_eip);
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void bx_instr_cnear_branch_not_taken(unsigned cpu);
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void bx_instr_ucnear_branch(unsigned cpu, unsigned what, bx_address new_eip);
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void bx_instr_far_branch(unsigned cpu, unsigned what, Bit16u new_cs, bx_address new_eip);
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void bx_instr_opcode(unsigned cpu, const Bit8u *opcode, unsigned len, bx_bool is32, bx_bool is64);
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void bx_instr_fetch_decode_completed(unsigned cpu, bxInstruction_c *i);
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void bx_instr_prefix(unsigned cpu, Bit8u prefix);
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void bx_instr_interrupt(unsigned cpu, unsigned vector);
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void bx_instr_exception(unsigned cpu, unsigned vector);
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void bx_instr_hwinterrupt(unsigned cpu, unsigned vector, Bit16u cs, bx_address eip);
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void bx_instr_mem_data_access(unsigned cpu, unsigned seg, bx_address offset, unsigned len, unsigned rw);
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/* simulation init, shutdown, reset */
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# define BX_INSTR_INIT(cpu_id) bx_instr_init(cpu_id)
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# define BX_INSTR_EXIT(cpu_id)
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# define BX_INSTR_RESET(cpu_id) bx_instr_reset(cpu_id)
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# define BX_INSTR_HLT(cpu_id)
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# define BX_INSTR_MWAIT(cpu_id, addr, len, flags)
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# define BX_INSTR_NEW_INSTRUCTION(cpu_id) bx_instr_new_instruction(cpu_id)
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/* called from command line debugger */
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# define BX_INSTR_DEBUG_PROMPT()
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# define BX_INSTR_START() bx_instr_start()
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# define BX_INSTR_STOP() bx_instr_stop()
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# define BX_INSTR_PRINT() bx_instr_print()
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/* branch resoultion */
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# define BX_INSTR_CNEAR_BRANCH_TAKEN(cpu_id, new_eip) bx_instr_cnear_branch_taken(cpu_id, new_eip)
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# define BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(cpu_id) bx_instr_cnear_branch_not_taken(cpu_id)
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# define BX_INSTR_UCNEAR_BRANCH(cpu_id, what, new_eip) bx_instr_ucnear_branch(cpu_id, what, new_eip)
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# define BX_INSTR_FAR_BRANCH(cpu_id, what, new_cs, new_eip) bx_instr_far_branch(cpu_id, what, new_cs, new_eip)
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/* decoding completed */
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# define BX_INSTR_OPCODE(cpu_id, opcode, len, is32, is64) \
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bx_instr_opcode(cpu_id, opcode, len, is32, is64)
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# define BX_INSTR_FETCH_DECODE_COMPLETED(cpu_id, i) \
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bx_instr_fetch_decode_completed(cpu_id, i)
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/* prefix byte decoded */
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# define BX_INSTR_PREFIX(cpu_id, prefix) bx_instr_prefix(cpu_id, prefix)
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/* exceptional case and interrupt */
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# define BX_INSTR_EXCEPTION(cpu_id, vector) bx_instr_exception(cpu_id, vector)
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# define BX_INSTR_INTERRUPT(cpu_id, vector) bx_instr_interrupt(cpu_id, vector)
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# define BX_INSTR_HWINTERRUPT(cpu_id, vector, cs, eip) bx_instr_hwinterrupt(cpu_id, vector, cs, eip)
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/* TLB/CACHE control instruction executed */
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# define BX_INSTR_CLFLUSH(cpu_id, laddr, paddr)
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# define BX_INSTR_CACHE_CNTRL(cpu_id, what)
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# define BX_INSTR_TLB_CNTRL(cpu_id, what, new_cr3)
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# define BX_INSTR_PREFETCH_HINT(cpu_id, what, seg, offset)
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/* execution */
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# define BX_INSTR_BEFORE_EXECUTION(cpu_id, i)
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# define BX_INSTR_AFTER_EXECUTION(cpu_id, i)
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# define BX_INSTR_REPEAT_ITERATION(cpu_id, i)
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/* memory access */
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# define BX_INSTR_LIN_ACCESS(cpu_id, lin, phy, len, rw)
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/* memory access */
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# define BX_INSTR_MEM_DATA_ACCESS(cpu_id, seg, offset, len, rw) \
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bx_instr_mem_data_access(cpu_id, seg, offset, len, rw)
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/* called from memory object */
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# define BX_INSTR_PHY_WRITE(cpu_id, addr, len)
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# define BX_INSTR_PHY_READ(cpu_id, addr, len)
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/* feedback from device units */
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# define BX_INSTR_INP(addr, len)
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# define BX_INSTR_INP2(addr, len, val)
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# define BX_INSTR_OUTP(addr, len)
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# define BX_INSTR_OUTP2(addr, len, val)
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/* wrmsr callback */
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# define BX_INSTR_WRMSR(cpu_id, addr, value)
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#else
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/* simulation init, shutdown, reset */
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# define BX_INSTR_INIT(cpu_id)
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# define BX_INSTR_EXIT(cpu_id)
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# define BX_INSTR_RESET(cpu_id)
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# define BX_INSTR_HLT(cpu_id)
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# define BX_INSTR_MWAIT(cpu_id, addr, len, flags)
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# define BX_INSTR_NEW_INSTRUCTION(cpu_id)
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/* called from command line debugger */
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# define BX_INSTR_DEBUG_PROMPT()
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# define BX_INSTR_START()
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# define BX_INSTR_STOP()
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# define BX_INSTR_PRINT()
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/* branch resoultion */
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# define BX_INSTR_CNEAR_BRANCH_TAKEN(cpu_id, new_eip)
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# define BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(cpu_id)
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# define BX_INSTR_UCNEAR_BRANCH(cpu_id, what, new_eip)
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# define BX_INSTR_FAR_BRANCH(cpu_id, what, new_cs, new_eip)
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/* decoding completed */
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# define BX_INSTR_OPCODE(cpu_id, opcode, len, is32, is64)
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# define BX_INSTR_FETCH_DECODE_COMPLETED(cpu_id, i)
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/* prefix byte decoded */
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# define BX_INSTR_PREFIX(cpu_id, prefix)
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/* exceptional case and interrupt */
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# define BX_INSTR_EXCEPTION(cpu_id, vector)
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# define BX_INSTR_INTERRUPT(cpu_id, vector)
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# define BX_INSTR_HWINTERRUPT(cpu_id, vector, cs, eip)
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/* TLB/CACHE control instruction executed */
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# define BX_INSTR_CLFLUSH(cpu_id, laddr, paddr)
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# define BX_INSTR_CACHE_CNTRL(cpu_id, what)
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# define BX_INSTR_TLB_CNTRL(cpu_id, what, new_cr3)
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# define BX_INSTR_PREFETCH_HINT(cpu_id, what, seg, offset)
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/* execution */
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# define BX_INSTR_BEFORE_EXECUTION(cpu_id, i)
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# define BX_INSTR_AFTER_EXECUTION(cpu_id, i)
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# define BX_INSTR_REPEAT_ITERATION(cpu_id, i)
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/* memory access */
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# define BX_INSTR_LIN_ACCESS(cpu_id, lin, phy, len, rw)
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/* memory access */
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# define BX_INSTR_MEM_DATA_ACCESS(cpu_id, seg, offset, len, rw)
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/* called from memory object */
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# define BX_INSTR_PHY_WRITE(cpu_id, addr, len)
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# define BX_INSTR_PHY_READ(cpu_id, addr, len)
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/* feedback from device units */
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# define BX_INSTR_INP(addr, len)
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# define BX_INSTR_INP2(addr, len, val)
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# define BX_INSTR_OUTP(addr, len)
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# define BX_INSTR_OUTP2(addr, len, val)
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/* wrmsr callback */
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# define BX_INSTR_WRMSR(cpu_id, addr, value)
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#endif
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