Subversion Repositories zipcpu

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#

# Filename:     Makefile

#

# Project:      Zip CPU -- a small, lightweight, RISC CPU soft core

#

# Purpose:      This is a grand makefile for the entire project.  It will

#               build the assembler, and a Verilog testbench, and then

#               even test the CPU via that test bench.

#

#       Targets include:

#

#               bench   Build the CPP test bench/debugger facility.

#

#               rtl     Run Verilator on the RTL

#

#               sw      Build the assembler.

#

#               test    Run the test bench on the assembler test file.

#

#

# Creator:      Dan Gisselquist, Ph.D.

#               Gisselquist Tecnology, LLC

#

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#

# Copyright (C) 2015, Gisselquist Technology, LLC

#

# This program is free software (firmware): you can redistribute it and/or

# modify it under the terms of  the GNU General Public License as published

# by the Free Software Foundation, either version 3 of the License, or (at

# your option) any later version.

#

# This program is distributed in the hope that it will be useful, but WITHOUT

# ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or

# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

# for more details.

#

# License:      GPL, v3, as defined and found on www.gnu.org,

#               http://www.gnu.org/licenses/gpl.html

#

#

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#

.PHONY: all

all: rtl sw bench

.PHONY: rtl

rtl:

        cd rtl; make

.PHONY: sw

sw:

        cd sw/zasm; make

.PHONY: bench

bench:  rtl

        cd bench/cpp; make

test: sw rtl

        cd sw/zasm; make test

        cd bench/cpp; make test