OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [bench/] [asm/] [helloworld.S] - Blame information for rev 180

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 12 dgisselq
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2
;
3
; Filename:     helloworld.S
4
;
5
; Project:      Zip CPU -- a small, lightweight, RISC CPU soft core
6
;
7
; Purpose:      A test of whether or not we can scroll a message on a
8
;               seven segment display.  This depends upon the seven segment
9
;               display driver (not included) being installed at position
10
;               0x15 in memory.  If so, this scrolls the message:
11
;               "HELLO UJorld." across the 4 seven segment display digits.
12
;
13
;               This test discovered that right shifting by 31 or more did
14
;               not result in zero as desired.  It also discovered that the
15
;               .DAT assembly instruction did not function as desired.  Both
16
;               bugs were fixed to get this to work.
17
;
18
; Creator:      Dan Gisselquist, Ph.D.
19 69 dgisselq
;               Gisselquist Technology, LLC
20 12 dgisselq
;
21
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
22
;
23
; Copyright (C) 2015, Gisselquist Technology, LLC
24
;
25
; This program is free software (firmware): you can redistribute it and/or
26
; modify it under the terms of  the GNU General Public License as published
27
; by the Free Software Foundation, either version 3 of the License, or (at
28
; your option) any later version.
29
;
30
; This program is distributed in the hope that it will be useful, but WITHOUT
31
; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
32
; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
33
; for more details.
34
;
35
; License:      GPL, v3, as defined and found on www.gnu.org,
36
;               http://www.gnu.org/licenses/gpl.html
37
;
38
;
39
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
40
;
41
; Register map
42
;       R12 peripherals
43
;       R11  timer length
44
;       R10  value to clear/reset the PIC
45
;       uR12 = memory
46
;       uR11 = rawsseg
47
;       uR9  = state
48
;       R8   = new value for SSEG
49 150 dgisselq
        .file "helloworld.S"
50
        .text
51
        .globl  entry
52
        .org 0x2000
53
        .type   entry, @function
54
entry:
55 12 dgisselq
build_supervisor_state:
56 150 dgisselq
        .set peripheral_base, 0xc0000000<<2
57
        LDI     build_supervisor_state,R0
58
        LDI     peripheral_base,R12
59
        LDI     0xc0000000,R12  ; Load a pointer to our peripherals
60
        LDI     $0x5f5e1,R11    ; An amount to reset the timer to: 1/4 sec
61 12 dgisselq
        LSL     $6,R11
62 150 dgisselq
        LDI     0x8010ffff,R0   ; A value to clear/reset the PIC for timerA inst
63
        MOV     user_data(PC),uR12      ; User memory (so this isn't supervisor state..)
64
        ; BRA   $4
65
        BRA     build_user_state
66
user_data:
67
        .INT    0x6e9e1c1c      ; Raw SSEG for 'HELL'
68
        .INT    0xfc007c70      ; Raw SSEG for 'O UJ'
69
        .INT    0x3a0a607b      ; Raw SSEG for 'orld.'
70
        .INT    0x00000000      ; Raw SSEG for '    '
71
        .text
72 12 dgisselq
build_user_state:
73 150 dgisselq
        LDI     $0x15,R0
74 12 dgisselq
        MOV     R0,uR11
75 150 dgisselq
        MOV     user_task(PC),uPC
76 12 dgisselq
        CLR     R0
77
        MOV     R0,uR9
78
repeat:
79
        STO     R11,$4(R12)     ; Reset the timer
80
        STO     R10,(R12)       ; Reset the PIC
81
        RTU
82 150 dgisselq
        ; BRA   $-4
83
        BRA     repeat
84 12 dgisselq
user_task:
85
        MOV     R9,R0
86
        LSR     $2,R0
87
        ADD     R12,R0
88
        LOD     (R0),R8         ; Read the left word
89
        MOV     R9,R1           ; Rotate it into place
90
        AND     $3,R1
91
        LSL     $3,R1           ; Multiply by eight
92
        LSL     R1,R8           ; Shift words to left by 0,8,16,24 bits
93
 
94
        ADD     $1,R0           ; Calculate address of next word
95
        CMP     $4+R12,R0
96
        SUB.GE  $4,R0
97
        LOD     (R0),R2         ; Load the next word into a building location
98
        LDI     $32,R3
99
        SUB     R1,R3
100
        LSR     R3,R2
101
        OR      R2,R8           ; Put the two together
102
 
103
        STO     R8,(R11)        ; Store the result
104
 
105
        ADD     $1,R9           ; Increment our state
106
        AND     $15,R9
107
 
108
        WAIT                    ; Wait for the next interrupt
109 150 dgisselq
        ; BRA   $-21            ; Back up to the top to start over
110
        BRA     user_task
111 12 dgisselq
 
112
        BREAK
113
        BREAK
114
        BREAK
115 150 dgisselq
 
116
 
117
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.