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[/] [zipcpu/] [trunk/] [bench/] [asm/] [nullpc.s] - Blame information for rev 74

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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Filename:     nullpc.s
;
; Project:      Zip CPU -- a small, lightweight, RISC CPU soft core
;
; Purpose:      A quick test of whether or not the prefetch shuts down and
;               idles properly when given an invalid (NULL) address.  This is
;       intended to be run in the simulator (zippy_tb), as I don't know how I
;       would verify operation on a real device.
;
; Creator:      Dan Gisselquist, Ph.D.
;               Gisselquist Technology, LLC
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Copyright (C) 2015, Gisselquist Technology, LLC
;
; This program is free software (firmware): you can redistribute it and/or
; modify it under the terms of  the GNU General Public License as published
; by the Free Software Foundation, either version 3 of the License, or (at
; your option) any later version.
;
; This program is distributed in the hope that it will be useful, but WITHOUT
; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
; for more details.
;
; License:      GPL, v3, as defined and found on www.gnu.org,
;               http://www.gnu.org/licenses/gpl.html
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
start:
        CLR     R0
        CLR     R1
        CLR     R2
        CLR     R3
        CLR     R4
        MOV     R0,uR0
        MOV     R0,uR1
        MOV     R0,uR2
        MOV     R0,uR3
        MOV     R0,uR4
        MOV     user_start(PC),uPC
        MOV     R0,uCC
        RTU
        MOV     uCC,R0
        TST     0x100,R0
        BNZ     user_test_worked
        ; We could do a BUSY.Z, but then the simulator wouldn't have
        ; picked up our stop condition
        BUSY
user_test_worked:
        MOV     user_dive_test(PC),uPC
        RTU
        MOV     uCC,R0
        TST     0x0800,R0
        BRA     user_dive_worked
        BUSY
user_dive_worked:
        ; Finally, let's test whether or not a null address from supervisor
        ; mode halts the CPU as desired.
        JMP     R1
        NOOP
        NOOP
        ; HALT = success.  However, if we halt here we certainly don't have
        ; a success.  Hence, signal a test failure by calling a busy instruction
        BUSY
 
; Let's see if jumping to a null address creates the exception we want
user_start:
        JMP     R1
        NOOP
        NOOP
 
; How about divide by zero?
user_dive_test:
        LDI     25,R0
        CLR     R1
        CLR     R2
        DIVS    R1,R0
        ADD     1,R2
        ADD     1,R2
        ADD     1,R2
        ADD     1,R2
        ADD     1,R2
        BUSY

Line No.	Rev	Author	Line
1	74	dgisselq	`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
2			`;`
3			`; Filename: nullpc.s`
4			`;`
5			`; Project: Zip CPU -- a small, lightweight, RISC CPU soft core`
6			`;`
7			`; Purpose: A quick test of whether or not the prefetch shuts down and`
8			`; idles properly when given an invalid (NULL) address. This is`
9			`; intended to be run in the simulator (zippy_tb), as I don't know how I`
10			`; would verify operation on a real device.`
11			`;`
12			`; Creator: Dan Gisselquist, Ph.D.`
13			`; Gisselquist Technology, LLC`
14			`;`
15			`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
16			`;`
17			`; Copyright (C) 2015, Gisselquist Technology, LLC`
18			`;`
19			`; This program is free software (firmware): you can redistribute it and/or`
20			`; modify it under the terms of the GNU General Public License as published`
21			`; by the Free Software Foundation, either version 3 of the License, or (at`
22			`; your option) any later version.`
23			`;`
24			`; This program is distributed in the hope that it will be useful, but WITHOUT`
25			`; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
26			`; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
27			`; for more details.`
28			`;`
29			`; License: GPL, v3, as defined and found on www.gnu.org,`
30			`; http://www.gnu.org/licenses/gpl.html`
31			`;`
32			`;`
33			`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
34			`;`
35			`start:`
36			`CLR R0`
37			`CLR R1`
38			`CLR R2`
39			`CLR R3`
40			`CLR R4`
41			`MOV R0,uR0`
42			`MOV R0,uR1`
43			`MOV R0,uR2`
44			`MOV R0,uR3`
45			`MOV R0,uR4`
46			`MOV user_start(PC),uPC`
47			`MOV R0,uCC`
48			`RTU`
49			`MOV uCC,R0`
50			`TST 0x100,R0`
51			`BNZ user_test_worked`
52			`; We could do a BUSY.Z, but then the simulator wouldn't have`
53			`; picked up our stop condition`
54			`BUSY`
55			`user_test_worked:`
56			`MOV user_dive_test(PC),uPC`
57			`RTU`
58			`MOV uCC,R0`
59			`TST 0x0800,R0`
60			`BRA user_dive_worked`
61			`BUSY`
62			`user_dive_worked:`
63			`; Finally, let's test whether or not a null address from supervisor`
64			`; mode halts the CPU as desired.`
65			`JMP R1`
66			`NOOP`
67			`NOOP`
68			`; HALT = success. However, if we halt here we certainly don't have`
69			`; a success. Hence, signal a test failure by calling a busy instruction`
70			`BUSY`
71
72			`; Let's see if jumping to a null address creates the exception we want`
73			`user_start:`
74			`JMP R1`
75			`NOOP`
76			`NOOP`
77
78			`; How about divide by zero?`
79			`user_dive_test:`
80			`LDI 25,R0`
81			`CLR R1`
82			`CLR R2`
83			`DIVS R1,R0`
84			`ADD 1,R2`
85			`ADD 1,R2`
86			`ADD 1,R2`
87			`ADD 1,R2`
88			`ADD 1,R2`
89			`BUSY`

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[/] [zipcpu/] [trunk/] [bench/] [asm/] [nullpc.s] - Blame information for rev 74