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[/] [zipcpu/] [trunk/] [bench/] [asm/] [poptest.s] - Blame information for rev 93

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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Filename:     poptest.s
;
; Project:      Zip CPU -- a small, lightweight, RISC CPU soft core
;
; Purpose:      Testing whether or not the new popcount (POPC) and bit reversal
;               (BREV) operations work by using software to duplicate these
;       instructions and then comparing the software result to the actual
;       harddware result.  As of the first half billion values, this works.
;       (I'm still running on the rest ....)
;
; Creator:      Dan Gisselquist, Ph.D.
;               Gisselquist Technology, LLC
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Copyright (C) 2015, Gisselquist Technology, LLC
;
; This program is free software (firmware): you can redistribute it and/or
; modify it under the terms of  the GNU General Public License as published
; by the Free Software Foundation, either version 3 of the License, or (at
; your option) any later version.
;
; This program is distributed in the hope that it will be useful, but WITHOUT
; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
; for more details.
;
; License:      GPL, v3, as defined and found on www.gnu.org,
;               http://www.gnu.org/licenses/gpl.html
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
#define LFSRFILL        0x000001
#define LFSRTAPS        0x0408b85
master_entry:
        MOV     user_entry(PC),uPC
        MOV     stack(PC),uSP
        ;
        RTU
        ; 
        HALT
 
user_entry:
        ; LDI   LFSRFILL,R6
        ; LDI   LFSRTAPS,R7
        CLR     R6
        LDI     1,R7
        CLR     R8
        CLR     R12
 
function_test_loop:
        ; Pseudorandom number generator
        ; LSR   1,R6
        ; XOR.C R7,R6
 
        ; In order number generator
        ADD     R7,R6
 
        MOV     R6,R0
        ADD     1,R8
 
        POPC    R0,R4
        BREV    R0,R5
 
        MOV     2+__HERE__(PC),R1
        BRA     sw_pop_count
        CMP     R0,R4
        ADD.NZ  1,R12
        TRAP.NZ 0
 
        MOV     R6,R0
        MOV     2+__HERE__(PC),R1
        BRA     sw_reverse_bit_order
        CMP     R0,R5
        ADD.NZ  2,R12
        TRAP.NZ 0x01000
 
        ;       
        ; CMP   LFSRFILL,R6
        ; TRAP.Z        0
        ;
        CMP     0,R6
        TRAP.Z  0
 
        BRA     function_test_loop
 
 
sw_pop_count:
        ; On entry, R0 = value of interest
        ;               R1 = return address
        ; On exit, R0 = result
        ;               R1 = return address
        SUB     2,SP
        STO     R1,(SP)         ; R1 will be our loop counter
        STO     R2,1(SP)        ; R2 will be our accumulator and eventual result
        CLR     R2
sw_pop_count_loop:
        LSR     1,R0
        ADD.C   1,R2
        BZ      sw_pop_count_exit
        BRA     sw_pop_count_loop
sw_pop_count_exit:
        MOV     R2,R0
        LOD     (SP),R1
        LOD     1(SP),R2
        ADD     2,SP
        JMP     R1
 
 
 
sw_reverse_bit_order:
        ; On entry, R0 = value of interest
        ;               R1 = return address
        ; On exit, R0 = result
        ;               R1 = return address
        SUB     2,SP
        STO     R1,(SP)         ; R1 will be our loop counter
        STO     R2,1(SP)        ; R2 will be our accumulator and eventual result
        LDI     32,R1
        CLR     R2
reverse_bit_order_loop:
        LSL     1,R2
        LSR     1,R0
        OR.C    1,R2
        SUB     1,R1
        BZ      reverse_bit_order_exit
        BRA     reverse_bit_order_loop
reverse_bit_order_exit:
        MOV     R2,R0
        LOD     (SP),R1
        LOD     1(SP),R2
        ADD     2,SP
        JMP     R1
 
 
        fill    512,0
stack:  // Must point to a valid word initially
        word    0

Line No.	Rev	Author	Line
1	74	dgisselq	`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
2			`;`
3			`; Filename: poptest.s`
4			`;`
5			`; Project: Zip CPU -- a small, lightweight, RISC CPU soft core`
6			`;`
7			`; Purpose: Testing whether or not the new popcount (POPC) and bit reversal`
8			`; (BREV) operations work by using software to duplicate these`
9			`; instructions and then comparing the software result to the actual`
10			`; harddware result. As of the first half billion values, this works.`
11			`; (I'm still running on the rest ....)`
12			`;`
13			`; Creator: Dan Gisselquist, Ph.D.`
14			`; Gisselquist Technology, LLC`
15			`;`
16			`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
17			`;`
18			`; Copyright (C) 2015, Gisselquist Technology, LLC`
19			`;`
20			`; This program is free software (firmware): you can redistribute it and/or`
21			`; modify it under the terms of the GNU General Public License as published`
22			`; by the Free Software Foundation, either version 3 of the License, or (at`
23			`; your option) any later version.`
24			`;`
25			`; This program is distributed in the hope that it will be useful, but WITHOUT`
26			`; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
27			`; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
28			`; for more details.`
29			`;`
30			`; License: GPL, v3, as defined and found on www.gnu.org,`
31			`; http://www.gnu.org/licenses/gpl.html`
32			`;`
33			`;`
34			`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
35			`;`
36			`#define LFSRFILL 0x000001`
37			`#define LFSRTAPS 0x0408b85`
38			`master_entry:`
39			`MOV user_entry(PC),uPC`
40			`MOV stack(PC),uSP`
41			`;`
42			`RTU`
43			`;`
44			`HALT`
45
46			`user_entry:`
47			`; LDI LFSRFILL,R6`
48			`; LDI LFSRTAPS,R7`
49			`CLR R6`
50			`LDI 1,R7`
51			`CLR R8`
52			`CLR R12`
53
54			`function_test_loop:`
55			`; Pseudorandom number generator`
56			`; LSR 1,R6`
57			`; XOR.C R7,R6`
58
59			`; In order number generator`
60			`ADD R7,R6`
61
62			`MOV R6,R0`
63			`ADD 1,R8`
64
65			`POPC R0,R4`
66			`BREV R0,R5`
67
68			`MOV 2+__HERE__(PC),R1`
69			`BRA sw_pop_count`
70			`CMP R0,R4`
71			`ADD.NZ 1,R12`
72			`TRAP.NZ 0`
73
74			`MOV R6,R0`
75			`MOV 2+__HERE__(PC),R1`
76			`BRA sw_reverse_bit_order`
77			`CMP R0,R5`
78			`ADD.NZ 2,R12`
79			`TRAP.NZ 0x01000`
80
81			`;`
82			`; CMP LFSRFILL,R6`
83			`; TRAP.Z 0`
84			`;`
85			`CMP 0,R6`
86			`TRAP.Z 0`
87
88			`BRA function_test_loop`
89
90
91			`sw_pop_count:`
92			`; On entry, R0 = value of interest`
93			`; R1 = return address`
94			`; On exit, R0 = result`
95			`; R1 = return address`
96			`SUB 2,SP`
97			`STO R1,(SP) ; R1 will be our loop counter`
98			`STO R2,1(SP) ; R2 will be our accumulator and eventual result`
99			`CLR R2`
100			`sw_pop_count_loop:`
101			`LSR 1,R0`
102			`ADD.C 1,R2`
103			`BZ sw_pop_count_exit`
104			`BRA sw_pop_count_loop`
105			`sw_pop_count_exit:`
106			`MOV R2,R0`
107			`LOD (SP),R1`
108			`LOD 1(SP),R2`
109			`ADD 2,SP`
110			`JMP R1`
111
112
113
114			`sw_reverse_bit_order:`
115			`; On entry, R0 = value of interest`
116			`; R1 = return address`
117			`; On exit, R0 = result`
118			`; R1 = return address`
119			`SUB 2,SP`
120			`STO R1,(SP) ; R1 will be our loop counter`
121			`STO R2,1(SP) ; R2 will be our accumulator and eventual result`
122			`LDI 32,R1`
123			`CLR R2`
124			`reverse_bit_order_loop:`
125			`LSL 1,R2`
126			`LSR 1,R0`
127			`OR.C 1,R2`
128			`SUB 1,R1`
129			`BZ reverse_bit_order_exit`
130			`BRA reverse_bit_order_loop`
131			`reverse_bit_order_exit:`
132			`MOV R2,R0`
133			`LOD (SP),R1`
134			`LOD 1(SP),R2`
135			`ADD 2,SP`
136			`JMP R1`
137
138
139			`fill 512,0`
140			`stack: // Must point to a valid word initially`
141			`word 0`

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[/] [zipcpu/] [trunk/] [bench/] [asm/] [poptest.s] - Blame information for rev 93