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[/] [zipcpu/] [trunk/] [bench/] [asm/] [testdiv.S] - Blame information for rev 82

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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Filename:     testdiv.S
;
; Project:      Zip CPU -- a small, lightweight, RISC CPU soft core
;
; Purpose:      Tests the libraries signed division algorithm.
;
; Creator:      Dan Gisselquist, Ph.D.
;               Gisselquist Technology, LLC
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Copyright (C) 2015, Gisselquist Technology, LLC
;
; This program is free software (firmware): you can redistribute it and/or
; modify it under the terms of  the GNU General Public License as published
; by the Free Software Foundation, either version 3 of the License, or (at
; your option) any later version.
;
; This program is distributed in the hope that it will be useful, but WITHOUT
; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
; for more details.
;
; License:      GPL, v3, as defined and found on www.gnu.org,
;               http://www.gnu.org/licenses/gpl.html
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Registers:
;       R12     Peripheral base
;       R11     Address of our one memory variable
;
/* something else */
#include "sys.i"
start:
        LDI     0xc0000000,R12  ; Get the address of our peripheral base
        MOV     $1(PC),R11      ; Get a memory address for a variable
        BRA     skip_test_variable
test_variable:
        WORD    0
skip_test_variable:
        LDI     $-1,R0  ; Start the watchdog timer
        STO     R0,sys.bus.wdt(R12)
        LSR     $1,R0   ; R0 now = 0x7fffffff
        STO     R0,sys.bus.tma(R12)
        LSR     $1,R0   ; R0 now = 0x3fffffff
        STO     R0,sys.bus.tmb(R12)
        LSR     $1,R0
        STO     R0,sys.bus.tmc(R12)
        ;
        CLR     R0
wdt_test_loop:
        ADD     $1,R0
        LOD     (R11),R1
        CMP     R0,R1
        STO.LT  R0,(R11)
        TST     -1,R0
        BLT     wdt_test_program_is_broken
        BRA     wdt_test_loop
 
wdt_test_program_is_broken:
        HALT
 
 
 
 
 
 
 
 
 
 
entry:
        ; Set up a test program
        MOV     test_div_program(PC),uPC
        MOV     top_of_stack(PC),uSP
        ; Run it in user space
        RTU
        ; Check for how the result came back: R0 = 0 means success
        MOV     uR11,R11
        TST     -1,R11
        HALT.Z
        BUSY
 
test_div_program:
        ;
        LDI     1,R11
        LDI     5,R0
        LDI     1,R1
        LDI     5,R2
        LDI     0,R3
        MOV     __HERE__+2(PC),R4
        BRA     test_divs
 
        ;
        LDI     2,R11
        LDI     5,R0
        LDI     2,R1
        LDI     2,R2
        LDI     1,R3
        MOV     __HERE__+2(PC),R4
        BRA     test_divs
 
        ;
        LDI     3,R11
        LDI     0xb53d0,R0
        LDI     0x2d,R1
        LDI     16496,R2
        LDI     32,R3
        MOV     __HERE__+2(PC),R4
        BRA     test_divs
 
        ;
        LDI     4,R11
        LDI     2031890191,R0
        LDI     120193795,R1
        LDI     16,R2
        LDI     108789471,R3
        MOV     __HERE__+2(PC),R4
        BRA     test_divs
 
        ;
        LDI     5,R11
        LDI     203553,R0
        LDI     142580994,R1
        LDI     0,R2
        LDI     203553,R3
        MOV     __HERE__+2(PC),R4
        BRA     test_divs
 
        ;
        LDI     6,R11
        LDI     142580994,R0
        LDI     203553,R1
        LDI     700,R2
        LDI     93894,R3
        MOV     __HERE__+2(PC),R4
        BRA     test_divs
 
        ;
        LDI     7,R11
        LDI     142580994,R0
        LDI     2499,R1
        LDI     57055,R2
        LDI     549,R3
        MOV     __HERE__+2(PC),R4
        BRA     test_divs
 
        ;
        LDI     8,R11
        LDI     -142580994,R0
        LDI     2499,R1
        LDI     -57055,R2
        LDI     -549,R3
        MOV     __HERE__+2(PC),R4
        BRA     test_divs
 
        ;
        LDI     9,R11
        LDI     142580994,R0
        LDI     -2499,R1
        LDI     -57055,R2
        LDI     549,R3
        MOV     __HERE__+2(PC),R4
        BRA     test_divs
 
        ;
        LDI     10,R11
        LDI     -142580994,R0
        LDI     -2499,R1
        LDI     57055,R2
        LDI     -549,R3
        MOV     __HERE__+2(PC),R4
        BRA     test_divs
 
        ;
        CLR     R11
        TRAP    0
 
test_divs:
        ;       R0 = Numerator
        ;       R1 = Denominator
        ;       R2 = Integer result
        ;       R3 = Remainder
        ;       R4 = Return address
        ;       R11= Test failure ID
        MOV     R2,R5
        MOV     R3,R6
        MOV     __HERE__+2(PC),R2
        BRA     lib_divs
        CMP     R0,R5
        BNZ     test_failure
        CMP     R1,R6
        BNZ     test_failure
        JMP     R4
 
test_failure:
        TRAP    0
        NOOP
        BUSY
 

Line No.	Rev	Author	Line
1	50	dgisselq	`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
2			`;`
3			`; Filename: testdiv.S`
4			`;`
5			`; Project: Zip CPU -- a small, lightweight, RISC CPU soft core`
6			`;`
7			`; Purpose: Tests the libraries signed division algorithm.`
8			`;`
9			`; Creator: Dan Gisselquist, Ph.D.`
10	69	dgisselq	`; Gisselquist Technology, LLC`
11	50	dgisselq	`;`
12			`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
13			`;`
14			`; Copyright (C) 2015, Gisselquist Technology, LLC`
15			`;`
16			`; This program is free software (firmware): you can redistribute it and/or`
17			`; modify it under the terms of the GNU General Public License as published`
18			`; by the Free Software Foundation, either version 3 of the License, or (at`
19			`; your option) any later version.`
20			`;`
21			`; This program is distributed in the hope that it will be useful, but WITHOUT`
22			`; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
23			`; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
24			`; for more details.`
25			`;`
26			`; License: GPL, v3, as defined and found on www.gnu.org,`
27			`; http://www.gnu.org/licenses/gpl.html`
28			`;`
29			`;`
30			`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
31			`;`
32			`; Registers:`
33			`; R12 Peripheral base`
34			`; R11 Address of our one memory variable`
35			`;`
36	69	dgisselq	`/* something else */`
37	50	dgisselq	`#include "sys.i"`
38			`start:`
39			`LDI 0xc0000000,R12 ; Get the address of our peripheral base`
40			`MOV $1(PC),R11 ; Get a memory address for a variable`
41			`BRA skip_test_variable`
42			`test_variable:`
43	69	dgisselq	`WORD 0`
44	50	dgisselq	`skip_test_variable:`
45			`LDI $-1,R0 ; Start the watchdog timer`
46			`STO R0,sys.bus.wdt(R12)`
47			`LSR $1,R0 ; R0 now = 0x7fffffff`
48			`STO R0,sys.bus.tma(R12)`
49			`LSR $1,R0 ; R0 now = 0x3fffffff`
50			`STO R0,sys.bus.tmb(R12)`
51			`LSR $1,R0`
52			`STO R0,sys.bus.tmc(R12)`
53			`;`
54			`CLR R0`
55			`wdt_test_loop:`
56			`ADD $1,R0`
57			`LOD (R11),R1`
58			`CMP R0,R1`
59			`STO.LT R0,(R11)`
60			`TST -1,R0`
61			`BLT wdt_test_program_is_broken`
62			`BRA wdt_test_loop`
63
64			`wdt_test_program_is_broken:`
65			`HALT`
66
67
68
69
70
71
72
73
74
75
76	41	dgisselq	`entry:`
77			`; Set up a test program`
78			`MOV test_div_program(PC),uPC`
79			`MOV top_of_stack(PC),uSP`
80			`; Run it in user space`
81			`RTU`
82			`; Check for how the result came back: R0 = 0 means success`
83			`MOV uR11,R11`
84			`TST -1,R11`
85			`HALT.Z`
86			`BUSY`
87
88			`test_div_program:`
89			`;`
90			`LDI 1,R11`
91			`LDI 5,R0`
92			`LDI 1,R1`
93			`LDI 5,R2`
94			`LDI 0,R3`
95	69	dgisselq	`MOV __HERE__+2(PC),R4`
96	41	dgisselq	`BRA test_divs`
97
98			`;`
99			`LDI 2,R11`
100			`LDI 5,R0`
101			`LDI 2,R1`
102			`LDI 2,R2`
103			`LDI 1,R3`
104	69	dgisselq	`MOV __HERE__+2(PC),R4`
105	41	dgisselq	`BRA test_divs`
106
107			`;`
108			`LDI 3,R11`
109			`LDI 0xb53d0,R0`
110			`LDI 0x2d,R1`
111			`LDI 16496,R2`
112			`LDI 32,R3`
113	69	dgisselq	`MOV __HERE__+2(PC),R4`
114	41	dgisselq	`BRA test_divs`
115
116			`;`
117			`LDI 4,R11`
118			`LDI 2031890191,R0`
119			`LDI 120193795,R1`
120			`LDI 16,R2`
121			`LDI 108789471,R3`
122	69	dgisselq	`MOV __HERE__+2(PC),R4`
123	41	dgisselq	`BRA test_divs`
124
125			`;`
126			`LDI 5,R11`
127			`LDI 203553,R0`
128			`LDI 142580994,R1`
129			`LDI 0,R2`
130			`LDI 203553,R3`
131	69	dgisselq	`MOV __HERE__+2(PC),R4`
132	41	dgisselq	`BRA test_divs`
133
134			`;`
135			`LDI 6,R11`
136			`LDI 142580994,R0`
137			`LDI 203553,R1`
138			`LDI 700,R2`
139			`LDI 93894,R3`
140	69	dgisselq	`MOV __HERE__+2(PC),R4`
141	41	dgisselq	`BRA test_divs`
142
143			`;`
144			`LDI 7,R11`
145			`LDI 142580994,R0`
146			`LDI 2499,R1`
147			`LDI 57055,R2`
148			`LDI 549,R3`
149	69	dgisselq	`MOV __HERE__+2(PC),R4`
150	41	dgisselq	`BRA test_divs`
151
152			`;`
153			`LDI 8,R11`
154			`LDI -142580994,R0`
155			`LDI 2499,R1`
156			`LDI -57055,R2`
157			`LDI -549,R3`
158	69	dgisselq	`MOV __HERE__+2(PC),R4`
159	41	dgisselq	`BRA test_divs`
160
161			`;`
162			`LDI 9,R11`
163			`LDI 142580994,R0`
164			`LDI -2499,R1`
165			`LDI -57055,R2`
166			`LDI 549,R3`
167	69	dgisselq	`MOV __HERE__+2(PC),R4`
168	41	dgisselq	`BRA test_divs`
169
170			`;`
171			`LDI 10,R11`
172			`LDI -142580994,R0`
173			`LDI -2499,R1`
174			`LDI 57055,R2`
175			`LDI -549,R3`
176	69	dgisselq	`MOV __HERE__+2(PC),R4`
177	41	dgisselq	`BRA test_divs`
178
179			`;`
180			`CLR R11`
181			`TRAP 0`
182
183			`test_divs:`
184			`; R0 = Numerator`
185			`; R1 = Denominator`
186			`; R2 = Integer result`
187			`; R3 = Remainder`
188	69	dgisselq	`; R4 = Return address`
189	41	dgisselq	`; R11= Test failure ID`
190	69	dgisselq	`MOV R2,R5`
191			`MOV R3,R6`
192			`MOV __HERE__+2(PC),R2`
193			`BRA lib_divs`
194			`CMP R0,R5`
195	41	dgisselq	`BNZ test_failure`
196	69	dgisselq	`CMP R1,R6`
197	41	dgisselq	`BNZ test_failure`
198	69	dgisselq	`JMP R4`
199	41	dgisselq
200			`test_failure:`
201			`TRAP 0`
202			`NOOP`
203			`BUSY`
204

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[/] [zipcpu/] [trunk/] [bench/] [asm/] [testdiv.S] - Blame information for rev 82