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[/] [zipcpu/] [trunk/] [bench/] [cpp/] [zippy_tb.cpp] - Blame information for rev 2

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1 2 dgisselq 
///////////////////////////////////////////////////////////////////////////////
2 
//
3 
// Filename:    zippy_tb.cpp
4 
//
5 
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6 
//
7 
// Purpose:     A bench simulator for the CPU.  Eventually, you should be
8 
//              able to give this program the name of a piece of compiled
9 
//              code to load into memory.  For now, we hand assemble with the
10 
//              computers help.
11 
//
12 
//
13 
// Creator:     Dan Gisselquist, Ph.D.
14 
//              Gisselquist Tecnology, LLC
15 
//
16 
///////////////////////////////////////////////////////////////////////////////
17 
//
18 
// Copyright (C) 2015, Gisselquist Technology, LLC
19 
//
20 
// This program is free software (firmware): you can redistribute it and/or
21 
// modify it under the terms of  the GNU General Public License as published
22 
// by the Free Software Foundation, either version 3 of the License, or (at
23 
// your option) any later version.
24 
//
25 
// This program is distributed in the hope that it will be useful, but WITHOUT
26 
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
27 
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
28 
// for more details.
29 
//
30 
// License:     GPL, v3, as defined and found on www.gnu.org,
31 
//              http://www.gnu.org/licenses/gpl.html
32 
//
33 
//
34 
///////////////////////////////////////////////////////////////////////////////
35 
//
36 
//
37 
#include <signal.h>
38 
#include <time.h>
39 
 
40 
#include <ctype.h>
41 
#include <ncurses.h>
42 
 
43 
#include "verilated.h"
44 
#include "Vzipsystem.h"
45 
 
46 
#include "testb.h"
47 
// #include "twoc.h"
48 
// #include "qspiflashsim.h"
49 
#include "memsim.h"
50 
#include "zopcodes.h"
51 
#include "zparser.h"
52 
 
53 
#define CMD_REG         0
54 
#define CMD_DATA        1
55 
#define CMD_HALT        (1<<10)
56 
#define CMD_STALL       (1<<9)
57 
#define CMD_STEP        (1<<8)
58 
#define CMD_INT         (1<<7)
59 
#define CMD_RESET       (1<<6)
60 
 
61 
 
62 
// No particular "parameters" need definition or redefinition here.
63 
class   ZIPPY_TB : public TESTB<Vzipsystem> {
64 
public:
65 
        unsigned long   m_tx_busy_count;
66 
        MEMSIM          m_mem;
67 
        // QSPIFLASHSIM m_flash;
68 
        FILE            *dbg_fp;
69 
        bool            dbg_flag, bomb;
70 
 
71 
        ZIPPY_TB(void) : m_mem(1<<20) {
72 
                //dbg_fp = fopen("dbg.txt", "w");
73 
                dbg_fp = NULL;
74 
                dbg_flag = false;
75 
                bomb = false;
76 
        }
77 
 
78 
        void    reset(void) {
79 
                // m_flash.debug(false);
80 
                TESTB<Vzipsystem>::reset();
81 
        }
82 
 
83 
        bool    on_tick(void) {
84 
                tick();
85 
                return true;
86 
        }
87 
 
88 
        void    showval(int y, int x, const char *lbl, unsigned int v) {
89 
                mvprintw(y,x, "%s: 0x%08x", lbl, v);
90 
        }
91 
 
92 
        void    dispreg(int y, int x, const char *n, unsigned int v) {
93 
                // 4,4,8,1 = 17 of 20, +3 = 19
94 
                mvprintw(y, x, "%s: 0x%08x", n, v);
95 
        }
96 
 
97 
        void    showreg(int y, int x, const char *n, int r) {
98 
                // 4,4,8,1 = 17 of 20, +3 = 19
99 
                mvprintw(y, x, "%s: 0x%08x", n, m_core->v__DOT__thecpu__DOT__regset[r]);
100 
                addch( ((r == m_core->v__DOT__thecpu__DOT__dcdA)
101 
                                &&(m_core->v__DOT__thecpu__DOT__dcdvalid)
102 
                                &&(m_core->v__DOT__thecpu__DOT__dcdA_rd))
103 
                        ?'a':' ');
104 
                addch( ((r == m_core->v__DOT__thecpu__DOT__dcdB)
105 
                                &&(m_core->v__DOT__thecpu__DOT__dcdvalid)
106 
                                &&(m_core->v__DOT__thecpu__DOT__dcdB_rd))
107 
                        ?'b':' ');
108 
                addch( ((r == m_core->v__DOT__thecpu__DOT__wr_reg_id)
109 
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce))
110 
                        ?'W':' ');
111 
        }
112 
 
113 
        void    showins(int y, const char *lbl, const int ce, const int valid,
114 
                        const int gie, const int stall, const unsigned int pc) {
115 
                char    line[80];
116 
 
117 
                if (ce)
118 
                        mvprintw(y, 0, "Ck ");
119 
                else
120 
                        mvprintw(y, 0, "   ");
121 
                if (stall)
122 
                        printw("Stl ");
123 
                else
124 
                        printw("    ");
125 
                printw("%s: 0x%08x", lbl, pc);
126 
 
127 
                if (valid) {
128 
                        if (gie) attroff(A_BOLD);
129 
                        else    attron(A_BOLD);
130 
                        zipi_to_string(m_mem[pc], line);
131 
                        printw("  %-20s", &line[1]);
132 
                } else {
133 
                        attroff(A_BOLD);
134 
                        printw("  (0x%08x)%28s", m_mem[pc],"");
135 
                }
136 
                attroff(A_BOLD);
137 
        }
138 
 
139 
        void    dbgins(const char *lbl, const int ce, const int valid,
140 
                        const int gie, const int stall, const unsigned int pc) {
141 
                char    line[80];
142 
 
143 
                if (!dbg_fp)
144 
                        return;
145 
 
146 
                if (ce)
147 
                        fprintf(dbg_fp, "%s Ck ", lbl);
148 
                else
149 
                        fprintf(dbg_fp, "%s    ", lbl);
150 
                if (stall)
151 
                        fprintf(dbg_fp, "Stl ");
152 
                else
153 
                        fprintf(dbg_fp, "    ");
154 
                fprintf(dbg_fp, "0x%08x:  ", pc);
155 
 
156 
                if (valid) {
157 
                        zipi_to_string(m_mem[pc], line);
158 
                        fprintf(dbg_fp, "  %-20s\n", &line[1]);
159 
                } else {
160 
                        fprintf(dbg_fp, "  (0x%08x)\n", m_mem[pc]);
161 
                }
162 
        }
163 
 
164 
        void    show_state(void) {
165 
                int     ln= 0;
166 
 
167 
                mvprintw(ln,0, "Peripherals-SS"); ln++;
168 
                /*
169 
                showval(ln, 1, "TRAP", m_core->v__DOT__trap_data);
170 
                        mvprintw(ln, 17, "%s%s",
171 
                                ((m_core->v__DOT__sys_cyc)
172 
                                &&(m_core->v__DOT__sys_we)
173 
                                &&(m_core->v__DOT__sys_addr == 0))?"W":" ",
174 
                                (m_core->v__DOT__trap_int)?"I":" ");
175 
                */
176 
                showval(ln, 1, "PIC ", m_core->v__DOT__pic_data);
177 
                showval(ln,21, "WDT ", m_core->v__DOT__watchdog__DOT__r_value);
178 
                showval(ln,41, "CACH", m_core->v__DOT__manualcache__DOT__cache_base);
179 
                showval(ln,61, "PIC2", m_core->v__DOT__ctri__DOT__r_int_state);
180 
 
181 
                ln++;
182 
                showval(ln, 1, "TMRA", m_core->v__DOT__timer_a__DOT__r_value);
183 
                showval(ln,21, "TMRB", m_core->v__DOT__timer_b__DOT__r_value);
184 
                showval(ln,41, "TMRB", m_core->v__DOT__timer_c__DOT__r_value);
185 
                showval(ln,61, "JIF ", m_core->v__DOT__jiffies__DOT__r_counter);
186 
 
187 
                ln++;
188 
                showval(ln, 1, "UTSK", m_core->v__DOT__utc_data);
189 
                showval(ln,21, "UMST", m_core->v__DOT__umc_data);
190 
                showval(ln,41, "UPST", m_core->v__DOT__upc_data);
191 
                showval(ln,61, "UAST", m_core->v__DOT__uac_data);
192 
 
193 
                ln++;
194 
                mvprintw(ln, 40, "%s %s",
195 
                        (m_core->v__DOT__cpu_halt)? "CPU-HALT": "        ",
196 
                        (m_core->v__DOT__cpu_reset)?"CPU-RESET":"         "); ln++;
197 
                mvprintw(ln, 40, "%s %s %s 0x%02x",
198 
                        (m_core->v__DOT__cmd_halt)? "HALT": "    ",
199 
                        (m_core->v__DOT__cmd_reset)?"RESET":"     ",
200 
                        (m_core->v__DOT__cmd_step)? "STEP" :"    ",
201 
                        (m_core->v__DOT__cmd_addr)&0x3f);
202 
                if (m_core->v__DOT__thecpu__DOT__gie)
203 
                        attroff(A_BOLD);
204 
                else
205 
                        attron(A_BOLD);
206 
                mvprintw(ln, 0, "Supervisor Registers");
207 
                ln++;
208 
 
209 
                showreg(ln, 1, "sR0 ", 0);
210 
                showreg(ln,21, "sR1 ", 1);
211 
                showreg(ln,41, "sR2 ", 2);
212 
                showreg(ln,61, "sR3 ", 3); ln++;
213 
 
214 
                showreg(ln, 1, "sR4 ", 4);
215 
                showreg(ln,21, "sR5 ", 5);
216 
                showreg(ln,41, "sR6 ", 6);
217 
                showreg(ln,61, "sR7 ", 7); ln++;
218 
 
219 
                showreg(ln, 1, "sR8 ",  8);
220 
                showreg(ln,21, "sR9 ",  9);
221 
                showreg(ln,41, "sR10", 10);
222 
                showreg(ln,61, "sR11", 11); ln++;
223 
 
224 
                showreg(ln, 1, "sR12", 12);
225 
                showreg(ln,21, "sSP ", 13);
226 
                mvprintw(ln,41, "sCC :%s%s%s%s%s%s%s",
227 
                        (m_core->v__DOT__thecpu__DOT__step)?"STP":"   ",
228 
                        (m_core->v__DOT__thecpu__DOT__sleep)?"SLP":"   ",
229 
                        (m_core->v__DOT__thecpu__DOT__gie)?"GIE":"   ",
230 
                        (m_core->v__DOT__thecpu__DOT__iflags&8)?"V":" ",
231 
                        (m_core->v__DOT__thecpu__DOT__iflags&4)?"N":" ",
232 
                        (m_core->v__DOT__thecpu__DOT__iflags&2)?"C":" ",
233 
                        (m_core->v__DOT__thecpu__DOT__iflags&1)?"Z":" ");
234 
                mvprintw(ln,61, "sPC : 0x%08x", m_core->v__DOT__thecpu__DOT__ipc);
235 
                ln++;
236 
 
237 
                if (m_core->v__DOT__thecpu__DOT__gie)
238 
                        attron(A_BOLD);
239 
                else
240 
                        attroff(A_BOLD);
241 
                mvprintw(ln, 0, "User Registers"); ln++;
242 
                showreg(ln, 1, "uR0 ", 16);
243 
                showreg(ln,21, "uR1 ", 17);
244 
                showreg(ln,41, "uR2 ", 18);
245 
                showreg(ln,61, "uR3 ", 19); ln++;
246 
 
247 
                showreg(ln, 1, "uR4 ", 20);
248 
                showreg(ln,21, "uR5 ", 21);
249 
                showreg(ln,41, "uR6 ", 22);
250 
                showreg(ln,61, "uR7 ", 23); ln++;
251 
 
252 
                showreg(ln, 1, "uR8 ", 24);
253 
                showreg(ln,21, "uR9 ", 25);
254 
                showreg(ln,41, "uR10", 26);
255 
                showreg(ln,61, "uR11", 27); ln++;
256 
 
257 
                showreg(ln, 1, "uR12", 28);
258 
                showreg(ln,21, "uSP ", 29);
259 
                mvprintw(ln,41, "uCC :%s%s%s%s%s%s%s",
260 
                        (m_core->v__DOT__thecpu__DOT__step)?"STP":"   ",
261 
                        (m_core->v__DOT__thecpu__DOT__sleep)?"SLP":"   ",
262 
                        (m_core->v__DOT__thecpu__DOT__gie)?"GIE":"   ",
263 
                        (m_core->v__DOT__thecpu__DOT__flags&8)?"V":" ",
264 
                        (m_core->v__DOT__thecpu__DOT__flags&4)?"N":" ",
265 
                        (m_core->v__DOT__thecpu__DOT__flags&2)?"C":" ",
266 
                        (m_core->v__DOT__thecpu__DOT__flags&1)?"Z":" ");
267 
                mvprintw(ln,61, "uPC : 0x%08x", m_core->v__DOT__thecpu__DOT__upc);
268 
 
269 
                attroff(A_BOLD);
270 
                ln+=1;
271 
 
272 
                mvprintw(ln, 0, "PFPIPE: rda=%08x/%d, bas=%08x, off=%08x, nv=%08x",
273 
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_addr,
274 
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cv,
275 
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_base,
276 
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_offset,
277 
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_nvalid);
278 
                ln++;
279 
                mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
280 
                        (m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":"   ",
281 
                        (m_core->v__DOT__thecpu__DOT__pf_stb)?"STB":"   ",
282 
                        "  ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":"  ",
283 
                        (m_core->v__DOT__thecpu__DOT__pf_addr),
284 
                        0, // (m_core->v__DOT__thecpu__DOT__pf_data),
285 
                        (m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":"   ",
286 
                        (m_core->v__DOT__cpu_stall)?"STL":"   ",
287 
                        (m_core->v__DOT__wb_data)); ln++;
288 
 
289 
                mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
290 
                        (m_core->v__DOT__thecpu__DOT__mem_cyc)?"CYC":"   ",
291 
                        (m_core->v__DOT__thecpu__DOT__mem_stb)?"STB":"   ",
292 
                        (m_core->v__DOT__thecpu__DOT__mem_we )?"WE":"  ",
293 
                        (m_core->v__DOT__thecpu__DOT__mem_addr),
294 
                        (m_core->v__DOT__thecpu__DOT__mem_data),
295 
                        (m_core->v__DOT__thecpu__DOT__mem_ack)?"ACK":"   ",
296 
                        (m_core->v__DOT__cpu_stall)?"STL":"   ",
297 
                        (m_core->v__DOT__thecpu__DOT__mem_result)); ln++;
298 
 
299 
                mvprintw(ln, 0, "SYSBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
300 
                        (m_core->o_wb_cyc)?"CYC":"   ",
301 
                        (m_core->o_wb_stb)?"STB":"   ",
302 
                        (m_core->o_wb_we )?"WE":"  ",
303 
                        (m_core->o_wb_addr),
304 
                        (m_core->o_wb_data),
305 
                        (m_core->i_wb_ack)?"ACK":"   ",
306 
                        (m_core->i_wb_stall)?"STL":"   ",
307 
                        (m_core->i_wb_data)); ln+=2;
308 
 
309 
                showins(ln, "I ",
310 
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
311 
                        m_core->v__DOT__thecpu__DOT__pf_valid,
312 
                        //m_core->v__DOT__thecpu__DOT__instruction_gie,
313 
                        m_core->v__DOT__thecpu__DOT__gie,
314 
                        0,
315 
                        // m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
316 
                        m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
317 
 
318 
                showins(ln, "Dc",
319 
                        m_core->v__DOT__thecpu__DOT__dcd_ce,
320 
                        m_core->v__DOT__thecpu__DOT__dcdvalid,
321 
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
322 
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
323 
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
324 
 
325 
                showins(ln, "Op",
326 
                        m_core->v__DOT__thecpu__DOT__op_ce,
327 
                        m_core->v__DOT__thecpu__DOT__opvalid,
328 
                        m_core->v__DOT__thecpu__DOT__op_gie,
329 
                        m_core->v__DOT__thecpu__DOT__op_stall,
330 
                        m_core->v__DOT__thecpu__DOT__op_pc-1); ln++;
331 
 
332 
                showins(ln, "Al",
333 
                        m_core->v__DOT__thecpu__DOT__alu_ce,
334 
                        m_core->v__DOT__thecpu__DOT__alu_pc_valid,
335 
                        m_core->v__DOT__thecpu__DOT__alu_gie,
336 
                        m_core->v__DOT__thecpu__DOT__alu_stall,
337 
                        m_core->v__DOT__thecpu__DOT__alu_pc-1); ln++;
338 
 
339 
                mvprintw(ln-4, 48,
340 
                        (m_core->v__DOT__thecpu__DOT__new_pc)?"new-pc":"      ");
341 
                printw("(%s:%02x,%x)",
342 
                        (m_core->v__DOT__thecpu__DOT__set_cond)?"SET":"   ",
343 
                        (m_core->v__DOT__thecpu__DOT__opF&0x0ff),
344 
                        (m_core->v__DOT__thecpu__DOT__op_gie)
345 
                                ?  (m_core->v__DOT__thecpu__DOT__w_uflags)
346 
                                : (m_core->v__DOT__thecpu__DOT__w_iflags));
347 
 
348 
                printw("(%s%s%s:%02x)",
349 
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"OF":"  ",
350 
                        (m_core->v__DOT__thecpu__DOT__alF_wr)?"FL":"  ",
351 
                        (m_core->v__DOT__thecpu__DOT__wr_flags_ce)?"W":" ",
352 
                        (m_core->v__DOT__thecpu__DOT__alu_flags));
353 
                /*
354 
                mvprintw(ln-3, 48, "dcdI : 0x%08x",
355 
                        m_core->v__DOT__thecpu__DOT__dcdI);
356 
                mvprintw(ln-2, 48, "r_opB: 0x%08x",
357 
                        m_core->v__DOT__thecpu__DOT__opB);
358 
                */
359 
                mvprintw(ln-3, 48, "Op(%x)%8x %8x->%08x",
360 
                        m_core->v__DOT__thecpu__DOT__opn,
361 
                        m_core->v__DOT__thecpu__DOT__opA,
362 
                        m_core->v__DOT__thecpu__DOT__opB,
363 
                        m_core->v__DOT__thecpu__DOT__alu_result);
364 
                mvprintw(ln-1, 48, "MEM: %s%s %s%s %s %-5s",
365 
                        (m_core->v__DOT__thecpu__DOT__opM)?"M":" ",
366 
                        (m_core->v__DOT__thecpu__DOT__mem_ce)?"CE":"  ",
367 
                        (m_core->v__DOT__thecpu__DOT__mem_we)?"Wr ":"Rd ",
368 
                        (m_core->v__DOT__thecpu__DOT__mem_stalled)?"PIPE":"    ",
369 
                        (m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV":"    ",
370 
                        zop_regstr[(m_core->v__DOT__thecpu__DOT__mem_wreg&0x1f)^0x10]);
371 
        }
372 
 
373 
        unsigned int    cmd_read(unsigned int a) {
374 
                if (dbg_fp) {
375 
                        dbg_flag= true;
376 
                        fprintf(dbg_fp, "CMD-READ(%d)\n", a);
377 
                }
378 
                wb_write(CMD_REG, CMD_HALT|(a&0x3f));
379 
                while((wb_read(CMD_REG) & CMD_STALL) == 0)
380 
                        ;
381 
                unsigned int v = wb_read(CMD_DATA);
382 
 
383 
                if (dbg_flag)
384 
                        fprintf(dbg_fp, "CMD-READ(%d) = 0x%08x\n", a,
385 
                                v);
386 
                dbg_flag = false;
387 
                return v;
388 
        }
389 
 
390 
        void    read_state(void) {
391 
                int     ln= 0;
392 
 
393 
                mvprintw(ln,0, "Peripherals-RS"); ln++;
394 
                showval(ln, 1, "PIC ", cmd_read(32+ 0));
395 
                showval(ln,21, "WDT ", cmd_read(32+ 1));
396 
                showval(ln,41, "CACH", cmd_read(32+ 2));
397 
                showval(ln,61, "PIC2", cmd_read(32+ 3));
398 
                ln++;
399 
                showval(ln, 1, "TMRA", cmd_read(32+ 4));
400 
                showval(ln,21, "TMRB", cmd_read(32+ 5));
401 
                showval(ln,41, "TMRC", cmd_read(32+ 6));
402 
                showval(ln,61, "JIF ", cmd_read(32+ 7));
403 
 
404 
                ln++;
405 
                showval(ln, 1, "UTSK", cmd_read(32+12));
406 
                showval(ln,21, "UMST", cmd_read(32+13));
407 
                showval(ln,41, "UPST", cmd_read(32+14));
408 
                showval(ln,61, "UAST", cmd_read(32+15));
409 
 
410 
                ln++;
411 
                ln++;
412 
                unsigned int cc = cmd_read(14);
413 
                if (dbg_fp) fprintf(dbg_fp, "CC = %08x, gie = %d\n", cc,
414 
                        m_core->v__DOT__thecpu__DOT__gie);
415 
                if (cc & 0x020)
416 
                        attroff(A_BOLD);
417 
                else
418 
                        attron(A_BOLD);
419 
                mvprintw(ln, 0, "Supervisor Registers");
420 
                ln++;
421 
 
422 
                dispreg(ln, 1, "sR0 ", cmd_read(0));
423 
                dispreg(ln,21, "sR1 ", cmd_read(1));
424 
                dispreg(ln,41, "sR2 ", cmd_read(2));
425 
                dispreg(ln,61, "sR3 ", cmd_read(3)); ln++;
426 
 
427 
                dispreg(ln, 1, "sR4 ", cmd_read(4));
428 
                dispreg(ln,21, "sR5 ", cmd_read(5));
429 
                dispreg(ln,41, "sR6 ", cmd_read(6));
430 
                dispreg(ln,61, "sR7 ", cmd_read(7)); ln++;
431 
 
432 
                dispreg(ln, 1, "sR8 ", cmd_read( 8));
433 
                dispreg(ln,21, "sR9 ", cmd_read( 9));
434 
                dispreg(ln,41, "sR10", cmd_read(10));
435 
                dispreg(ln,61, "sR11", cmd_read(11)); ln++;
436 
 
437 
                dispreg(ln, 1, "sR12", cmd_read(12));
438 
                dispreg(ln,21, "sSP ", cmd_read(13));
439 
 
440 
                mvprintw(ln,41, "sCC :%s%s%s%s%s%s%s",
441 
                        (cc & 0x040)?"STP":"   ",
442 
                        (cc & 0x020)?"GIE":"   ",
443 
                        (cc & 0x010)?"SLP":"   ",
444 
                        (cc&8)?"V":" ",
445 
                        (cc&4)?"N":" ",
446 
                        (cc&2)?"C":" ",
447 
                        (cc&1)?"Z":" ");
448 
                mvprintw(ln,61, "sPC : 0x%08x", cmd_read(15));
449 
                ln++;
450 
 
451 
                if (cc & 0x020)
452 
                        attron(A_BOLD);
453 
                else
454 
                        attroff(A_BOLD);
455 
                mvprintw(ln, 0, "User Registers"); ln++;
456 
                dispreg(ln, 1, "uR0 ", cmd_read(16));
457 
                dispreg(ln,21, "uR1 ", cmd_read(17));
458 
                dispreg(ln,41, "uR2 ", cmd_read(18));
459 
                dispreg(ln,61, "uR3 ", cmd_read(19)); ln++;
460 
 
461 
                dispreg(ln, 1, "uR4 ", cmd_read(20));
462 
                dispreg(ln,21, "uR5 ", cmd_read(21));
463 
                dispreg(ln,41, "uR6 ", cmd_read(22));
464 
                dispreg(ln,61, "uR7 ", cmd_read(23)); ln++;
465 
 
466 
                dispreg(ln, 1, "uR8 ", cmd_read(24));
467 
                dispreg(ln,21, "uR9 ", cmd_read(25));
468 
                dispreg(ln,41, "uR10", cmd_read(26));
469 
                dispreg(ln,61, "uR11", cmd_read(27)); ln++;
470 
 
471 
                dispreg(ln, 1, "uR12", cmd_read(28));
472 
                dispreg(ln,21, "uSP ", cmd_read(29));
473 
                cc = cmd_read(30);
474 
                mvprintw(ln,41, "uCC :%s%s%s%s%s%s%s",
475 
                        (cc&0x040)?"STP":"   ",
476 
                        (cc&0x020)?"GIE":"   ",
477 
                        (cc&0x010)?"SLP":"   ",
478 
                        (cc&8)?"V":" ",
479 
                        (cc&4)?"N":" ",
480 
                        (cc&2)?"C":" ",
481 
                        (cc&1)?"Z":" ");
482 
                mvprintw(ln,61, "uPC : 0x%08x", cmd_read(31));
483 
 
484 
                attroff(A_BOLD);
485 
                ln+=2;
486 
 
487 
                ln+=3;
488 
 
489 
                showins(ln, "I ",
490 
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
491 
                        m_core->v__DOT__thecpu__DOT__pf_valid,
492 
                        m_core->v__DOT__thecpu__DOT__gie,
493 
                        0,
494 
                        // m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
495 
                        m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
496 
 
497 
                showins(ln, "Dc",
498 
                        m_core->v__DOT__thecpu__DOT__dcd_ce,
499 
                        m_core->v__DOT__thecpu__DOT__dcdvalid,
500 
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
501 
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
502 
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
503 
 
504 
                showins(ln, "Op",
505 
                        m_core->v__DOT__thecpu__DOT__op_ce,
506 
                        m_core->v__DOT__thecpu__DOT__opvalid,
507 
                        m_core->v__DOT__thecpu__DOT__op_gie,
508 
                        m_core->v__DOT__thecpu__DOT__op_stall,
509 
                        m_core->v__DOT__thecpu__DOT__op_pc-1); ln++;
510 
 
511 
                showins(ln, "Al",
512 
                        m_core->v__DOT__thecpu__DOT__alu_ce,
513 
                        m_core->v__DOT__thecpu__DOT__alu_pc_valid,
514 
                        m_core->v__DOT__thecpu__DOT__alu_gie,
515 
                        m_core->v__DOT__thecpu__DOT__alu_stall,
516 
                        m_core->v__DOT__thecpu__DOT__alu_pc-1); ln++;
517 
        }
518 
        void    tick(void) {
519 
                int gie = m_core->v__DOT__thecpu__DOT__gie;
520 
                /*
521 
                m_core->i_qspi_dat = m_flash(m_core->o_qspi_cs_n,
522 
                                                m_core->o_qspi_sck,
523 
                                                m_core->o_qspi_dat);
524 
                */
525 
 
526 
                m_mem(m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
527 
                        m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
528 
                        m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
529 
 
530 
                if ((dbg_flag)&&(dbg_fp)) {
531 
                        fprintf(dbg_fp, "DBG  %s %s %s @0x%08x/%d[0x%08x] %s %s [0x%08x] %s %s %s%s%s%s%s%s%s%s\n",
532 
                                (m_core->i_dbg_cyc)?"CYC":"   ",
533 
                                (m_core->i_dbg_stb)?"STB":
534 
                                        ((m_core->v__DOT__dbg_stb)?"DBG":"   "),
535 
                                ((m_core->i_dbg_we)?"WE":"  "),
536 
                                (m_core->i_dbg_addr),0,
537 
                                m_core->i_dbg_data,
538 
                                (m_core->o_dbg_ack)?"ACK":"   ",
539 
                                (m_core->o_dbg_stall)?"STALL":"     ",
540 
                                (m_core->o_dbg_data),
541 
                                (m_core->v__DOT__cpu_halt)?"CPU-HALT ":"",
542 
                                (m_core->v__DOT__cpu_dbg_stall)?"CPU-DBG_STALL":"",
543 
                                (m_core->v__DOT__thecpu__DOT__dcdvalid)?"DCDV ":"",
544 
                                (m_core->v__DOT__thecpu__DOT__opvalid)?"OPV ":"",
545 
                                (m_core->v__DOT__thecpu__DOT__pf_cyc)?"PCYC ":"",
546 
                                (m_core->v__DOT__thecpu__DOT__mem_cyc)?"MCYC ":"",
547 
                                (m_core->v__DOT__thecpu__DOT__alu_wr)?"ALUW ":"",
548 
                                (m_core->v__DOT__thecpu__DOT__alu_ce)?"ALCE ":"",
549 
                                (m_core->v__DOT__thecpu__DOT__alu_valid)?"ALUV ":"",
550 
                                (m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV ":"");
551 
                        fprintf(dbg_fp, " SYS %s %s %s @0x%08x/%d[0x%08x] %s [0x%08x]\n",
552 
                                (m_core->v__DOT__sys_cyc)?"CYC":"   ",
553 
                                (m_core->v__DOT__sys_stb)?"STB":"   ",
554 
                                (m_core->v__DOT__sys_we)?"WE":"  ",
555 
                                (m_core->v__DOT__sys_addr),
556 
                                (m_core->v__DOT__dbg_addr),
557 
                                (m_core->v__DOT__sys_data),
558 
                                (m_core->v__DOT__dbg_ack)?"ACK":"   ",
559 
                                (m_core->v__DOT__wb_data));
560 
                }
561 
 
562 
                if (dbg_fp)
563 
                        fprintf(dbg_fp, "CEs %d/0x%08x,%d/0x%08x DCD: ->%02x, OP: ->%02x, ALU: halt=%d,%d ce=%d, valid=%d, wr=%d  Reg=%02x, IPC=%08x, UPC=%08x\n",
564 
                                m_core->v__DOT__thecpu__DOT__dcd_ce,
565 
                                m_core->v__DOT__thecpu__DOT__dcd_pc,
566 
                                m_core->v__DOT__thecpu__DOT__op_ce,
567 
                                m_core->v__DOT__thecpu__DOT__op_pc,
568 
                                m_core->v__DOT__thecpu__DOT__dcdA,
569 
                                m_core->v__DOT__thecpu__DOT__opR,
570 
                                m_core->v__DOT__cmd_halt,
571 
                                m_core->v__DOT__cpu_halt,
572 
                                m_core->v__DOT__thecpu__DOT__alu_ce,
573 
                                m_core->v__DOT__thecpu__DOT__alu_valid,
574 
                                m_core->v__DOT__thecpu__DOT__alu_wr,
575 
                                m_core->v__DOT__thecpu__DOT__alu_reg,
576 
                                m_core->v__DOT__thecpu__DOT__ipc,
577 
                                m_core->v__DOT__thecpu__DOT__upc);
578 
 
579 
                if ((dbg_fp)&&(!gie)&&(m_core->v__DOT__thecpu__DOT__w_release_from_interrupt)) {
580 
                        fprintf(dbg_fp, "RELEASE: int=%d, %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d\n",
581 
                                m_core->v__DOT__pic_interrupt,
582 
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
583 
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
584 
                                m_core->v__DOT__thecpu__DOT__wr_reg_vl,
585 
                                m_core->v__DOT__cmd_addr,
586 
                                m_core->v__DOT__dbg_idata,
587 
                                m_core->v__DOT__thecpu__DOT__master_ce,
588 
                                m_core->v__DOT__thecpu__DOT__alu_wr,
589 
                                m_core->v__DOT__thecpu__DOT__alu_valid,
590 
                                m_core->v__DOT__thecpu__DOT__mem_valid);
591 
                } else if ((dbg_fp)&&(gie)&&(m_core->v__DOT__thecpu__DOT__w_switch_to_interrupt)) {
592 
                        fprintf(dbg_fp, "SWITCH: %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d, F%02x,%02x\n",
593 
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
594 
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
595 
                                m_core->v__DOT__thecpu__DOT__wr_reg_vl,
596 
                                m_core->v__DOT__cmd_addr,
597 
                                m_core->v__DOT__dbg_idata,
598 
                                m_core->v__DOT__thecpu__DOT__master_ce,
599 
                                m_core->v__DOT__thecpu__DOT__alu_wr,
600 
                                m_core->v__DOT__thecpu__DOT__alu_valid,
601 
                                m_core->v__DOT__thecpu__DOT__mem_valid,
602 
                                m_core->v__DOT__thecpu__DOT__w_iflags,
603 
                                m_core->v__DOT__thecpu__DOT__w_uflags);
604 
                        fprintf(dbg_fp, "\tbrk=%d,%d\n",
605 
                                m_core->v__DOT__thecpu__DOT__break_en,
606 
                                m_core->v__DOT__thecpu__DOT__op_break);
607 
                }
608 
 
609 
                TESTB<Vzipsystem>::tick();
610 
                if ((dbg_fp)&&(gie != m_core->v__DOT__thecpu__DOT__gie)) {
611 
                        fprintf(dbg_fp, "SWITCH FROM %s to %s: sPC = 0x%08x uPC = 0x%08x pf_pc = 0x%08x\n",
612 
                                (gie)?"User":"Supervisor",
613 
                                (gie)?"Supervisor":"User",
614 
                                m_core->v__DOT__thecpu__DOT__ipc,
615 
                                m_core->v__DOT__thecpu__DOT__upc,
616 
                                m_core->v__DOT__thecpu__DOT__pf_pc);
617 
                } if (dbg_fp) {
618 
                        dbgins("Op - ", m_core->v__DOT__thecpu__DOT__op_ce,
619 
                                m_core->v__DOT__thecpu__DOT__opvalid,
620 
                                m_core->v__DOT__thecpu__DOT__op_gie,
621 
                                m_core->v__DOT__thecpu__DOT__op_stall,
622 
                                m_core->v__DOT__thecpu__DOT__op_pc-1);
623 
                        dbgins("Al - ",
624 
                                m_core->v__DOT__thecpu__DOT__alu_ce,
625 
                                m_core->v__DOT__thecpu__DOT__alu_pc_valid,
626 
                                m_core->v__DOT__thecpu__DOT__alu_gie,
627 
                                m_core->v__DOT__thecpu__DOT__alu_stall,
628 
                                m_core->v__DOT__thecpu__DOT__alu_pc-1);
629 
 
630 
                }
631 
 
632 
                if (m_core->v__DOT__cpu_dbg_we) {
633 
                        printf("WRITE-ENABLE!!\n");
634 
                        bomb = true;
635 
                }
636 
        }
637 
 
638 
        bool    test_success(void) {
639 
                return ((!m_core->v__DOT__thecpu__DOT__gie)
640 
                        &&(m_core->v__DOT__thecpu__DOT__sleep));
641 
        }
642 
 
643 
        bool    test_failure(void) {
644 
                return ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
645 
                        &&(!m_core->v__DOT__thecpu__DOT__alu_gie)
646 
                        &&(m_mem[m_core->v__DOT__thecpu__DOT__alu_pc-1]
647 
                                == 0x2f0f7fff));
648 
        }
649 
 
650 
        void    wb_write(unsigned a, unsigned int v) {
651 
                mvprintw(0,35, "%40s", "");
652 
                mvprintw(0,40, "wb_write(%d,%x)", a, v);
653 
                m_core->i_dbg_cyc = 1;
654 
                m_core->i_dbg_stb = 1;
655 
                m_core->i_dbg_we  = 1;
656 
                m_core->i_dbg_addr = a & 1;
657 
                m_core->i_dbg_data = v;
658 
 
659 
                tick();
660 
                while(m_core->o_dbg_stall)
661 
                        tick();
662 
 
663 
                m_core->i_dbg_stb = 0;
664 
                while(!m_core->o_dbg_ack)
665 
                        tick();
666 
 
667 
                // Release the bus
668 
                m_core->i_dbg_cyc = 0;
669 
                m_core->i_dbg_stb = 0;
670 
                tick();
671 
                mvprintw(0,35, "%40s", "");
672 
                mvprintw(0,40, "wb_write -- complete");
673 
        }
674 
 
675 
        unsigned long   wb_read(unsigned a) {
676 
                unsigned int    v;
677 
                mvprintw(0,35, "%40s", "");
678 
                mvprintw(0,40, "wb_read(0x%08x)", a);
679 
                m_core->i_dbg_cyc = 1;
680 
                m_core->i_dbg_stb = 1;
681 
                m_core->i_dbg_we  = 0;
682 
                m_core->i_dbg_addr = a & 1;
683 
 
684 
                tick();
685 
                while(m_core->o_dbg_stall)
686 
                        tick();
687 
 
688 
                m_core->i_dbg_stb = 0;
689 
                while(!m_core->o_dbg_ack)
690 
                        tick();
691 
                v = m_core->o_dbg_data;
692 
 
693 
                // Release the bus
694 
                m_core->i_dbg_cyc = 0;
695 
                m_core->i_dbg_stb = 0;
696 
                tick();
697 
 
698 
                mvprintw(0,35, "%40s", "");
699 
                mvprintw(0,40, "wb_read = 0x%08x", v);
700 
 
701 
                return v;
702 
        }
703 
 
704 
};
705 
 
706 
 
707 
int     main(int argc, char **argv) {
708 
        Verilated::commandArgs(argc, argv);
709 
        ZIPPY_TB        *tb = new ZIPPY_TB();
710 
        ZPARSER         zp;
711 
 
712 
        printf("uCC = %d\n", (int)zp.ZIP_uCC);
713 
        printf("MOV CC,R0 = 0x%08x\n", zp.op_mov(0,zp.ZIP_uCC, zp.ZIP_R0));
714 
                // = 0x200e8000
715 
                // Op = 0x2
716 
                // Result = 0x0, R0 (Supervisor/default)
717 
                // Cond   = 0x0
718 
                // BReg   = 0xe (CC)
719 
                // BMap   = 1, BReg = uCC
720 
                //
721 
 
722 
        initscr();
723 
        raw();
724 
        noecho();
725 
        keypad(stdscr, true);
726 
 
727 
        // mem[0x00000] = 0xbe000010; // Halt instruction
728 
        unsigned int mptr = 0;
729 
        /*
730 
        tb->m_mem[mptr++] = 0x30000000; //  0: CLR R0
731 
        tb->m_mem[mptr++] = 0x21000000; //  1: MOV R0,R1
732 
        tb->m_mem[mptr++] = 0x22000001; //  2: MOV $1+R0,R2
733 
        tb->m_mem[mptr++] = 0x23000002; //  3: MOV $2+R0,R3
734 
        tb->m_mem[mptr++] = 0x24000022; //  4: MOV $22h+R0,R4
735 
        tb->m_mem[mptr++] = 0x25100377; //  5: MOV $377h+R0,uR5
736 
        tb->m_mem[mptr++] = 0x4e000000; //  6: NOOP
737 
        tb->m_mem[mptr++] = 0xa0120000; //  7: ADD R2,R0
738 
        tb->m_mem[mptr++] = 0xa0000020; //  8: ADD $32,R0
739 
        tb->m_mem[mptr++] = 0xa00fffdf; //  9: ADD -$33,R0
740 
        tb->m_mem[mptr++] = 0xc02fffff; //  A: NOT.Z R0
741 
        tb->m_mem[mptr++] = 0xc0100000; //  B: CLRF R0
742 
        tb->m_mem[mptr++] = 0x31000005; //  C: LDI $5,R1
743 
        tb->m_mem[mptr++] = 0x00110000; //  D: CMP R0,R1
744 
        tb->m_mem[mptr++] = 0xc0afffff; //  E: NOT.LT R0
745 
        tb->m_mem[mptr++] = 0xc1cfffff; //  F: NOT.GE R1
746 
        tb->m_mem[mptr++] = 0x621ffff9; // 10: LOD $-7(PC),R2
747 
        tb->m_mem[mptr++] = 0x4f13dead; // 11: LODIHI $deadh,R3
748 
        tb->m_mem[mptr++] = 0x4f03beef; // 12: LODILO $beefh,R3
749 
        tb->m_mem[mptr++] = 0x731f0002; // 13: STO R3,$2(PC)
750 
        */
751 
 
752 
        /*
753 
        tb->m_mem[mptr++] = zp.op_clr(zp::ZIP_R12);//  0: CLR R12
754 
        tb->m_mem[mptr++] = 0x4f1cc000; //  1: LODIHI $c000h,R12
755 
        tb->m_mem[mptr++] = 0x2c1c0000; //  2: MOV R12,uR12
756 
        tb->m_mem[mptr++] = 0x2f1f000a; //  3: MOV $12+PC,uPC
757 
        tb->m_mem[mptr++] = 0x4f108001; //  4: LODIHI $8001,R0 // Turn on trap
758 
        tb->m_mem[mptr++] = 0x4f00ffff; //  5: LODILO $ffff,R0 // interrupts
759 
        tb->m_mem[mptr++] = 0x701c0001; //  6: STO R0,$1(R12)
760 
        tb->m_mem[mptr++] = 0xbe000020; //  7: RTU      // Switch to user mode
761 
        tb->m_mem[mptr++] = 0x601c0000; //  8: LOD (R12),R0 // Check the result
762 
        tb->m_mem[mptr++] = 0x00000000; //  A: CMP $0,R0
763 
        tb->m_mem[mptr++] = 0x2f4f0001; //  B: BNZ $1+PC
764 
        tb->m_mem[mptr++] = 0xbe000010; //  C: HALT     // On SUCCESS
765 
        tb->m_mem[mptr++] = 0x2f0f7fff; //  D: BRA PC-1 // On FAILURE
766 
        */
767 
 
768 
 
769 
        tb->m_mem[mptr++] = zp.op_clr(zp.ZIP_R0); //  0: CLR R0
770 
        tb->m_mem[mptr++] = zp.op_mov(zp.ZIP_R0,zp.ZIP_R1); //  1: MOV R0,R1
771 
        tb->m_mem[mptr++] = zp.op_mov(1,zp.ZIP_R0,zp.ZIP_R2); //  2: MOV $1+R0,R2
772 
        tb->m_mem[mptr++] = zp.op_mov(2,zp.ZIP_R0,zp.ZIP_R3); //  3: MOV $2+R0,R3
773 
        tb->m_mem[mptr++] = zp.op_mov(0x022, zp.ZIP_R0, zp.ZIP_R4); //  4: MOV $22h+R0,R4
774 
        tb->m_mem[mptr++] = zp.op_mov(0x377, zp.ZIP_R0, zp.ZIP_uR5); //  5: MOV $377h+R0,uR5
775 
        tb->m_mem[mptr++] = zp.op_noop(); //  6: NOOP
776 
        tb->m_mem[mptr++] = zp.op_add(0,zp.ZIP_R2,zp.ZIP_R0); //  7: ADD R2,R0
777 
        tb->m_mem[mptr++] = zp.op_add(32,zp.ZIP_R0); //  8: ADD $32,R0
778 
        tb->m_mem[mptr++] = zp.op_add(-33,zp.ZIP_R0); //  9: ADD -$33,R0
779 
        tb->m_mem[mptr++] = zp.op_not(zp.ZIPC_Z, zp.ZIP_R0); //  A: NOT.Z R0
780 
        tb->m_mem[mptr++] = zp.op_clrf(zp.ZIP_R0); //  B: CLRF R0
781 
        tb->m_mem[mptr++] = zp.op_ldi(5,zp.ZIP_R1); //  C: LDI $5,R1
782 
        tb->m_mem[mptr++] = zp.op_cmp(0,zp.ZIP_R0,zp.ZIP_R1); //  D: CMP R0,R1
783 
        tb->m_mem[mptr++] = zp.op_not(zp.ZIPC_LT, zp.ZIP_R0); //  E: NOT.LT R0
784 
        tb->m_mem[mptr++] = zp.op_not(zp.ZIPC_GE, zp.ZIP_R1); //  F: NOT.GE R1
785 
        tb->m_mem[mptr++] = zp.op_lod(-7,zp.ZIP_PC, zp.ZIP_R2); // 10: LOD $-7(PC),R2
786 
        tb->m_mem[mptr++] = zp.op_ldihi(0xdead, zp.ZIP_R3); // 11: LODIHI $deadh,R3
787 
        tb->m_mem[mptr++] = zp.op_ldilo(0xbeef, zp.ZIP_R3); // 12: LODILO $beefh,R3
788 
 
789 
        // Let's build a software test bench.
790 
        tb->m_mem[mptr++] = zp.op_clr(zp.ZIP_R12);//  0: CLR R12
791 
        tb->m_mem[mptr++] = zp.op_ldihi(0xc000,zp.ZIP_R12);
792 
        tb->m_mem[mptr++] = zp.op_mov(zp.ZIP_R12,zp.ZIP_uR12);
793 
        tb->m_mem[mptr++] = zp.op_mov(10,zp.ZIP_PC,zp.ZIP_uPC);
794 
        tb->m_mem[mptr++] = zp.op_clr(zp.ZIP_R0); // Clear R0, and disable ints
795 
        tb->m_mem[mptr++] = zp.op_sto(zp.ZIP_R0,0,zp.ZIP_R12);
796 
        tb->m_mem[mptr++] = zp.op_rtu(); //  7: RTU     // Switch to user mode
797 
        tb->m_mem[mptr++] = zp.op_mov(0,zp.ZIP_uCC, zp.ZIP_R0); // Check result
798 
        tb->m_mem[mptr++] = zp.op_tst(-256,zp.ZIP_R0);
799 
        tb->m_mem[mptr++] = zp.op_bnz(1);
800 
        tb->m_mem[mptr++] = zp.op_halt();// On SUCCESS
801 
        tb->m_mem[mptr++] = zp.op_busy(); // On FAILURE
802 
 
803 
 
804 
        // Now for a series of tests.  If the test fails, call the trap
805 
        // interrupt with the test number that failed.  Upon completion,
806 
        // call the trap with #0.
807 
 
808 
        // Now for a series of tests.  If the test fails, call the trap
809 
        // interrupt with the test number that failed.  Upon completion,
810 
        // call the trap with #0.
811 
 
812 
        // Test LDI to PC
813 
        // Some data registers
814 
        tb->m_mem[mptr] = mptr + 5 + 0x0100000; mptr++;
815 
        tb->m_mem[mptr++] = zp.op_ldi(0x020,zp.ZIP_CC); //  LDI $GIE,CC
816 
        tb->m_mem[mptr++] = zp.op_ldi(0x0200,zp.ZIP_R11); //  LDI $200h,R11
817 
        tb->m_mem[mptr++] = zp.op_lod(-4,zp.ZIP_PC,zp.ZIP_PC); //  1: LOD $-3(PC),PC
818 
        tb->m_mem[mptr++] = zp.op_clr(zp.ZIP_R11); //  2: CLR R11
819 
        tb->m_mem[mptr++] = zp.op_noop(); //  3: NOOP
820 
        tb->m_mem[mptr++] = zp.op_cmp(0,zp.ZIP_R11); //  4: CMP $0,R11
821 
        tb->m_mem[mptr++] = zp.op_mov(zp.ZIPC_Z, 0, zp.ZIP_R11,zp.ZIP_R10); //  5: STO.Z R11,(R12)
822 
        tb->m_mem[mptr++] = zp.op_mov(zp.ZIPC_Z, 0, zp.ZIP_R11,zp.ZIP_CC); //  5: STO.Z R11,(R12)
823 
        tb->m_mem[mptr++] = zp.op_add(1,zp.ZIP_R0); //  6: ADD $1,R0
824 
        tb->m_mem[mptr++] = zp.op_add(1,zp.ZIP_R0); //  7: ADD $1,R0
825 
 
826 
        // Let's test whether overflow works
827 
        tb->m_mem[mptr++] = zp.op_ldi(0x0300,zp.ZIP_R11); //  0: LDI $3,R11
828 
        tb->m_mem[mptr++] = zp.op_ldi(-1,zp.ZIP_R0); //  1: LDI $-1,R0
829 
        tb->m_mem[mptr++] = zp.op_lsr(1,zp.ZIP_R0); //  R0 // R0 = max int
830 
        tb->m_mem[mptr++] = zp.op_add(1,zp.ZIP_R0); //  Should set ovfl
831 
        tb->m_mem[mptr++] = zp.op_bv(1); //  4: BV $1+PC
832 
        tb->m_mem[mptr++] = zp.op_mov(0,zp.ZIP_R11, zp.ZIP_CC); // FAIL! if here
833 
        // Overflow set from subtraction
834 
        tb->m_mem[mptr++] = zp.op_ldi(0x0400,zp.ZIP_R11); //  6: LDI $4,R11
835 
        tb->m_mem[mptr++] = zp.op_ldi(1,zp.ZIP_R0); //  7: LDI $1,R0
836 
        tb->m_mem[mptr++] = 0x5000001f; //  8: ROL $31,R0
837 
        tb->m_mem[mptr++] = zp.op_sub(1,zp.ZIP_R0); // Should set ovfl
838 
        tb->m_mem[mptr++] = zp.op_bv(1); //  A: BV $1+PC
839 
        tb->m_mem[mptr++] = zp.op_mov(0,zp.ZIP_R11, zp.ZIP_CC); // FAIL! if here
840 
        // Overflow set from LSR
841 
        tb->m_mem[mptr++] = zp.op_ldi(0x0500,zp.ZIP_R11); //  C: LDI $5,R11
842 
        tb->m_mem[mptr++] = zp.op_ldi(1,zp.ZIP_R0); //  D: LDI $1,R0
843 
        tb->m_mem[mptr++] = 0x5000001f; //  E: ROL $31,R0
844 
        tb->m_mem[mptr++] = zp.op_lsr(1,zp.ZIP_R0); //  F: LSR $1,R0
845 
        tb->m_mem[mptr++] = zp.op_bv(1); //  A: BV $1+PC
846 
        tb->m_mem[mptr++] = zp.op_mov(0,zp.ZIP_R11, zp.ZIP_CC); // FAIL! if here
847 
        // Overflow set from LSL
848 
        tb->m_mem[mptr++] = zp.op_ldi(0x0600,zp.ZIP_R11); //  C: LDI $6,R11
849 
        tb->m_mem[mptr++] = zp.op_ldi(1,zp.ZIP_R0); //  D: LDI $1,R0
850 
        tb->m_mem[mptr++] = 0x5000001e; //  E: ROL $30,R0
851 
        tb->m_mem[mptr++] = zp.op_lsl(1,zp.ZIP_R0); //  F: LSR $1,R0
852 
        tb->m_mem[mptr++] = zp.op_bv(1); //  A: BV $1+PC
853 
        tb->m_mem[mptr++] = zp.op_mov(0,zp.ZIP_R11, zp.ZIP_CC); // FAIL! if here
854 
        // Overflow set from LSL, negative to positive
855 
        tb->m_mem[mptr++] = zp.op_ldi(0x0700,zp.ZIP_R11); //  C: LDI $7,R11
856 
        tb->m_mem[mptr++] = zp.op_ldi(1,zp.ZIP_R0); //  D: LDI $1,R0
857 
        tb->m_mem[mptr++] = 0x5000001f; //  E: ROL $30,R0
858 
        tb->m_mem[mptr++] = zp.op_lsl(1,zp.ZIP_R0); //  F: LSR $1,R0
859 
        tb->m_mem[mptr++] = zp.op_bv(1); //  A: BV $1+PC
860 
        tb->m_mem[mptr++] = zp.op_mov(0,zp.ZIP_R11, zp.ZIP_CC); // FAIL! if here
861 
 
862 
 
863 
        // Test carry
864 
        tb->m_mem[mptr++] = zp.op_ldi(0x01000, zp.ZIP_R11); //  0: LDI $16,R11
865 
        tb->m_mem[mptr++] = zp.op_ldi(-1, zp.ZIP_R0); //  1: LDI $-1,R0
866 
        tb->m_mem[mptr++] = zp.op_add(1, zp.ZIP_R0); //  2: ADD $1,R0
867 
        tb->m_mem[mptr++] = zp.op_tst(2, zp.ZIP_CC); //  3: TST $2,CC // Is the carry set?
868 
        tb->m_mem[mptr++] = zp.op_mov(zp.ZIPC_Z,0,zp.ZIP_R11, zp.ZIP_CC); // FAIL! if here
869 
        // and carry from subtraction
870 
        tb->m_mem[mptr++] = zp.op_ldi(0x01100, zp.ZIP_R11); //  0: LDI $17,R11
871 
        tb->m_mem[mptr++] = zp.op_sub(1, zp.ZIP_R0); //  1: SUB $1,R0
872 
        tb->m_mem[mptr++] = zp.op_tst(2, zp.ZIP_CC); //  2: TST $2,CC // Is the carry set?
873 
        tb->m_mem[mptr++] = zp.op_mov(zp.ZIPC_Z,0,zp.ZIP_R11, zp.ZIP_CC); // FAIL! if here
874 
 
875 
 
876 
 
877 
        // Let's try a loop: for i=0; i<5; i++)
878 
        //      We'll use R0=i, Immediates for 5
879 
        tb->m_mem[mptr++] = zp.op_ldi(0x01200, zp.ZIP_R11); //  0: LDI $18,R11
880 
        tb->m_mem[mptr++] = zp.op_clr(zp.ZIP_R0); //  0: CLR R0
881 
        tb->m_mem[mptr++] = zp.op_noop();
882 
        tb->m_mem[mptr++] = zp.op_add(1, zp.ZIP_R0); //  2: R0 = R0 + 1
883 
        tb->m_mem[mptr++] = zp.op_cmp(5, zp.ZIP_R0); //  3: CMP $5,R0
884 
        tb->m_mem[mptr++] = zp.op_blt(-4); //  4: BLT PC-4
885 
        //
886 
        // Let's try a reverse loop.  Such loops are usually cheaper to
887 
        // implement, and this one is no different: 2 loop instructions
888 
        // (minus setup instructions) vs 3 from before.
889 
        // R0 = 5; (from before)
890 
        // do {
891 
        // } while (R0 > 0);
892 
        tb->m_mem[mptr++] = zp.op_ldi(0x01300, zp.ZIP_R11); //  0: LDI $18,R11
893 
        tb->m_mem[mptr++] = zp.op_noop(); //  5: NOOP
894 
        tb->m_mem[mptr++] = zp.op_sub( 1, zp.ZIP_R0); //  6: R0 = R0 - 1
895 
        tb->m_mem[mptr++] = zp.op_bgt(-3); //  7: BGT PC-3
896 
        // How about the same thing with a >= comparison?
897 
        // R1 = 5; // Need to do this explicitly
898 
        // do {
899 
        // } while(R1 >= 0);
900 
        tb->m_mem[mptr++] = zp.op_ldi(0x01400, zp.ZIP_R11); //  0: LDI $18,R11
901 
        tb->m_mem[mptr++] = zp.op_ldi(5, zp.ZIP_R1);
902 
        tb->m_mem[mptr++] = zp.op_noop();
903 
        tb->m_mem[mptr++] = zp.op_sub(1, zp.ZIP_R1);
904 
        tb->m_mem[mptr++] = zp.op_bge(-3);
905 
 
906 
        // Let's try the reverse loop again, only this time we'll store our
907 
        // loop variable in memory.
908 
        // R0 = 5; (from before)
909 
        // do {
910 
        // } while (R0 > 0);
911 
        tb->m_mem[mptr++] = zp.op_ldi(0x01500, zp.ZIP_R11); //  0: LDI $18,R11
912 
        tb->m_mem[mptr++] = zp.op_bra(1); // Give us a memory location
913 
        tb->m_mem[mptr++] = 5; // Loop five times
914 
        tb->m_mem[mptr++] = zp.op_mov(-2, zp.ZIP_PC, zp.ZIP_R1); // Get var adr
915 
        tb->m_mem[mptr++] = zp.op_clr(zp.ZIP_R2);
916 
        tb->m_mem[mptr++] = zp.op_ldi(5, zp.ZIP_R0);
917 
        tb->m_mem[mptr++] = zp.op_sto(zp.ZIP_R0,0,zp.ZIP_R1);
918 
        tb->m_mem[mptr++] = zp.op_add(1,zp.ZIP_R2);
919 
        tb->m_mem[mptr++] = zp.op_add(14,zp.ZIP_R0);
920 
        tb->m_mem[mptr++] = zp.op_lod(0,zp.ZIP_R1,zp.ZIP_R0);
921 
        tb->m_mem[mptr++] = zp.op_sub( 1, zp.ZIP_R0);
922 
        tb->m_mem[mptr++] = zp.op_bgt(-6);
923 
        tb->m_mem[mptr++] = zp.op_cmp( 5, zp.ZIP_R2);
924 
        tb->m_mem[mptr++] = zp.op_mov(zp.ZIPC_NZ, 0, zp.ZIP_R11, zp.ZIP_CC);
925 
 
926 
        // Return success / Test the trap interrupt
927 
        tb->m_mem[mptr++] = zp.op_clr(zp.ZIP_R11); //  0: CLR R11
928 
        tb->m_mem[mptr++] = zp.op_mov(zp.ZIP_R11, zp.ZIP_CC);
929 
        tb->m_mem[mptr++] = zp.op_noop(); //  2: NOOP // Give it a chance to take
930 
        tb->m_mem[mptr++] = zp.op_noop(); //  3: NOOP // effect
931 
 
932 
        // Go into an infinite loop if the trap fails
933 
        // Permanent loop instruction -- a busy halt if you will
934 
        tb->m_mem[mptr++] = zp.op_busy(); //  4: BRA PC-1
935 
 
936 
        // And, in case we miss a halt ...
937 
        tb->m_mem[mptr++] = zp.op_halt(); // HALT
938 
 
939 
        tb->reset();
940 
        int     chv = 'q';
941 
        const   bool    live_debug_mode = true;
942 
 
943 
        if (live_debug_mode) {
944 
                bool    done = false, halted = true, manual = true;
945 
 
946 
                halfdelay(1);
947 
                tb->wb_write(CMD_REG, CMD_HALT | CMD_RESET);
948 
                // while((tb->wb_read(CMD_REG) & (CMD_HALT|CMD_STALL))==(CMD_HALT|CMD_STALL))
949 
                        // tb->show_state();
950 
 
951 
                while(!done) {
952 
                        chv = getch();
953 
                        switch(chv) {
954 
                        case 'h': case 'H':
955 
                                tb->wb_write(CMD_REG, CMD_HALT);
956 
                                if (!halted)
957 
                                        erase();
958 
                                halted = true;
959 
                                break;
960 
                        case 'g': case 'G':
961 
                                tb->wb_write(CMD_REG, 0);
962 
                                if (halted)
963 
                                        erase();
964 
                                halted = false;
965 
                                manual = false;
966 
                                break;
967 
                        case 'q': case 'Q':
968 
                                done = true;
969 
                                break;
970 
                        case 'r': case 'R':
971 
                                tb->wb_write(CMD_REG, CMD_RESET|CMD_HALT);
972 
                                halted = true;
973 
                                erase();
974 
                                break;
975 
                        case 's': case 'S':
976 
                                tb->wb_write(CMD_REG, CMD_STEP);
977 
                                manual = false;
978 
                                break;
979 
                        case 't': case 'T':
980 
                                manual = true;
981 
                                tb->tick();
982 
                                break;
983 
                        case ERR:
984 
                        default:
985 
                                if (!manual)
986 
                                        tb->tick();
987 
                        }
988 
 
989 
                        if (manual) {
990 
                                tb->show_state();
991 
                        } else if (halted) {
992 
                                if (tb->dbg_fp)
993 
                                        fprintf(tb->dbg_fp, "\n\nREAD-STATE ******\n");
994 
                                tb->read_state();
995 
                        } else
996 
                                tb->show_state();
997 
 
998 
                        if (tb->m_core->i_rst)
999 
                                done =true;
1000 
                        if (tb->bomb)
1001 
                                done = true;
1002 
                }
1003 
 
1004 
        } else { // Manual stepping mode
1005 
                tb->show_state();
1006 
 
1007 
                while('q' != tolower(chv = getch())) {
1008 
                        tb->tick();
1009 
                        tb->show_state();
1010 
 
1011 
                        if (tb->test_success())
1012 
                                break;
1013 
                        else if (tb->test_failure())
1014 
                                break;
1015 
                }
1016 
        }
1017 
 
1018 
        endwin();
1019 
 
1020 
        if (tb->test_success())
1021 
                printf("SUCCESS!\n");
1022 
        else if (tb->test_failure())
1023 
                printf("TEST FAILED!\n");
1024 
        else if (chv == 'q')
1025 
                printf("chv = %c\n", chv);
1026 
        exit(0);
1027 
}
1028 
 

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