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dgisselq |
################################################################################
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##
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## Filename: Makefile
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##
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## Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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##
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## Purpose: To direct the formal verification of particular components of
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## the ZipCPU.
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##
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## Targets: The default target, all, tests all of the components within
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## this module.
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##
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## Creator: Dan Gisselquist, Ph.D.
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## Gisselquist Technology, LLC
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##
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################################################################################
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##
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## Copyright (C) 2017-2019, Gisselquist Technology, LLC
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##
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## This program is free software (firmware): you can redistribute it and/or
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## modify it under the terms of the GNU General Public License as published
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## by the Free Software Foundation, either version 3 of the License, or (at
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## your option) any later version.
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##
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## This program is distributed in the hope that it will be useful, but WITHOUT
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## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License along
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## with this program. (It's in the $(ROOT)/doc directory. Run make with no
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## target there if the PDF file isn't present.) If not, see
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## for a copy.
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##
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## License: GPL, v3, as defined and found on www.gnu.org,
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## http://www.gnu.org/licenses/gpl.html
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##
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##
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################################################################################
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##
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##
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TESTS := prefetch dblfetch pfcache memops pipemem idecode div
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TESTS += zipmmu ziptimer zipcounter zipjiffies wbwatchdog zipmmu icontrol wbdmac
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TESTS += busdelay wbpriarbiter wbdblpriarb cpuops cpu dcache zipcpu
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.PHONY: $(TESTS)
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all: $(TESTS)
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RTL := ../../rtl
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SMTBMC := yosys-smtbmc
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# SOLVER := -s z3
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SOLVER := -s yices
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# SOLVER := -s boolector
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BMCARGS := --presat $(SOLVER)
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INDARGS := $(SOLVER) -i
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PFONE := prefetch
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PFTWO := dblfetch
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PFCACHE:= pfcache
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WBDLY := busdelay
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PRIARB := wbpriarbiter
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DBL := wbdblpriarb
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PIPE := pipemem
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MEM := memops
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MMU := zipmmu
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TMR := ziptimer
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CNT := zipcounter
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JIF := zipjiffies
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WDG := wbwatchdog
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INT := icontrol
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DCD := idecode
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DMA := wbdmac
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ALU := cpuops
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DIV := div
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CPU := zipcpu
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DCACHE := dcache
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.PHONY: cpu
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cpu: zipcpu
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MASTER := $(RTL)/ex/fwb_master.v
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SLAVE := $(RTL)/ex/fwb_slave.v
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.PHONY: $(PFONE)
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$(PFONE) : $(PFONE)/PASS
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$(PFONE)/PASS: $(PFONE).sby $(RTL)/core/$(PFONE).v $(MASTER)
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sby -f $(PFONE).sby
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.PHONY: $(PFTWO)
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$(PFTWO) : $(PFTWO)/PASS
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$(PFTWO)/PASS: $(PFTWO).sby $(RTL)/core/$(PFTWO).v $(MASTER)
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sby -f $(PFTWO).sby
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.PHONY: $(PFCACHE)
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$(PFCACHE): $(PFCACHE)_prf/PASS $(PFCACHE)_cvr/PASS
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$(PFCACHE)_prf/PASS: $(PFCACHE).sby $(RTL)/core/$(PFCACHE).v $(MASTER)
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sby -f $(PFCACHE).sby prf
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$(PFCACHE)_cvr/PASS: $(PFCACHE).sby $(RTL)/core/$(PFCACHE).v $(MASTER)
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sby -f $(PFCACHE).sby cvr
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.PHONY: $(WBDLY)
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$(WBDLY): $(WBDLY)/PASS
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$(WBDLY)/PASS: $(WBDLY).sby $(RTL)/ex/$(WBDLY).v $(MASTER) $(SLAVE)
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sby -f $(WBDLY).sby
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.PHONY: $(PRIARB)
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$(PRIARB): $(PRIARB)/PASS
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$(PRIARB)/PASS: $(PRIARB).sby $(RTL)/ex/$(PRIARB).v $(MASTER) $(SLAVE)
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sby -f $(PRIARB).sby
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.PHONY: $(DBL)
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$(DBL): $(DBL)/PASS
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$(DBL)/PASS: $(DBL).sby $(RTL)/ex/$(DBL).v $(MASTER) $(SLAVE) $(DBL).ys
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sby -f $(DBL).sby
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.PHONY: $(MEM)
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$(MEM): $(MEM)_cover/PASS $(MEM)_proof/PASS
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$(MEM)_proof/PASS: $(MEM).sby $(RTL)/core/$(MEM).v $(MASTER)
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sby -f $(MEM).sby proof
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$(MEM)_cover/PASS: $(MEM).sby $(RTL)/core/$(MEM).v $(MASTER)
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sby -f $(MEM).sby cover
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.PHONY: $(PIPE)
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$(PIPE): $(PIPE)_lcl_aligned_lock/PASS
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$(PIPE): $(PIPE)_lcl_aligned_nolock/PASS
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$(PIPE): $(PIPE)_lcl_noaligned_lock/PASS
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$(PIPE): $(PIPE)_lcl_noaligned_nolock/PASS
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$(PIPE): $(PIPE)_nolcl_aligned_lock/PASS
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$(PIPE): $(PIPE)_nolcl_aligned_nolock/PASS
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$(PIPE): $(PIPE)_nolcl_noaligned_lock/PASS
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$(PIPE): $(PIPE)_nolcl_noaligned_nolock/PASS
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$(PIPE)_lcl_aligned_lock/PASS: $(PIPE).sby $(RTL)/core/$(PIPE).v $(MASTER)
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sby -f $(PIPE).sby lcl_aligned_lock
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$(PIPE)_lcl_aligned_nolock/PASS: $(PIPE).sby $(RTL)/core/$(PIPE).v $(MASTER)
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sby -f $(PIPE).sby lcl_aligned_nolock
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$(PIPE)_lcl_noaligned_lock/PASS: $(PIPE).sby $(RTL)/core/$(PIPE).v $(MASTER)
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sby -f $(PIPE).sby lcl_noaligned_lock
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$(PIPE)_lcl_noaligned_nolock/PASS: $(PIPE).sby $(RTL)/core/$(PIPE).v $(MASTER)
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sby -f $(PIPE).sby lcl_noaligned_nolock
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$(PIPE)_nolcl_aligned_lock/PASS: $(PIPE).sby $(RTL)/core/$(PIPE).v $(MASTER)
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sby -f $(PIPE).sby nolcl_aligned_lock
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$(PIPE)_nolcl_aligned_nolock/PASS: $(PIPE).sby $(RTL)/core/$(PIPE).v $(MASTER)
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sby -f $(PIPE).sby nolcl_aligned_nolock
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$(PIPE)_nolcl_noaligned_lock/PASS: $(PIPE).sby $(RTL)/core/$(PIPE).v $(MASTER)
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sby -f $(PIPE).sby nolcl_noaligned_lock
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$(PIPE)_nolcl_noaligned_nolock/PASS: $(PIPE).sby $(RTL)/core/$(PIPE).v $(MASTER)
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sby -f $(PIPE).sby nolcl_noaligned_nolock
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.PHONY: $(MMU)
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$(MMU): $(MMU)/PASS
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$(MMU)/PASS: $(MMU).sby $(RTL)/peripherals/$(MMU).v $(MASTER) $(SLAVE)
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sby -f $(MMU).sby
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.PHONY: $(TMR)
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$(TMR): $(TMR)/PASS
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$(TMR)/PASS: $(TMR).sby $(RTL)/peripherals/$(TMR).v $(SLAVE) $(TMR).ys
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sby -f $(TMR).sby
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.PHONY: $(CNT)
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$(CNT): $(CNT)/PASS
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$(CNT)/PASS: $(CNT).sby $(RTL)/peripherals/$(CNT).v $(SLAVE)
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sby -f $(CNT).sby
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.PHONY: $(JIF)
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$(JIF): $(JIF)/PASS
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$(JIF)/PASS: $(JIF).sby $(RTL)/peripherals/$(JIF).v $(SLAVE)
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sby -f $(JIF).sby
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.PHONY: $(WDG)
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$(WDG): $(WDG)/PASS
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$(WDG)/PASS: $(WDG).sby $(RTL)/peripherals/$(WDG).v $(SLAVE)
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sby -f $(WDG).sby
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.PHONY: $(INT)
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$(INT): $(INT)/PASS
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$(INT)/PASS: $(INT).sby $(RTL)/peripherals/$(INT).v $(SLAVE)
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sby -f $(INT).sby
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.PHONY: $(DCD)
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$(DCD): $(DCD)_pipe_div_mpy_cis_opipe/PASS
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$(DCD): $(DCD)_pipe_div_mpy_cis_nopipe/PASS
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$(DCD): $(DCD)_pipe_div_mpy_nocis_pipe/PASS
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$(DCD): $(DCD)_pipe_div_mpy_nocis_nopipe/PASS
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$(DCD): $(DCD)_pipe_div_nompy_nocis_nopipe/PASS
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$(DCD): $(DCD)_pipe_nodiv_nompy_nocis_nopipe/PASS
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$(DCD): $(DCD)_nopipe_nodiv_nompy_nocis_nopipe/PASS
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$(DCD)_pipe_div_mpy_cis_opipe/PASS: $(RTL)/core/$(DCD).v $(DCD).sby f_idecode.v
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sby -f $(DCD).sby pipe_div_mpy_cis_opipe
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$(DCD)_pipe_div_mpy_cis_nopipe/PASS: $(RTL)/core/$(DCD).v $(DCD).sby f_idecode.v
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sby -f $(DCD).sby pipe_div_mpy_cis_nopipe
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$(DCD)_pipe_div_mpy_nocis_pipe/PASS: $(RTL)/core/$(DCD).v $(DCD).sby f_idecode.v
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sby -f $(DCD).sby pipe_div_mpy_nocis_pipe
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$(DCD)_pipe_div_mpy_nocis_nopipe/PASS: $(RTL)/core/$(DCD).v $(DCD).sby f_idecode.v
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sby -f $(DCD).sby pipe_div_mpy_nocis_nopipe
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$(DCD)_pipe_div_nompy_nocis_nopipe/PASS: $(RTL)/core/$(DCD).v $(DCD).sby f_idecode.v
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sby -f $(DCD).sby pipe_div_nompy_nocis_nopipe
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$(DCD)_pipe_nodiv_nompy_nocis_nopipe/PASS: $(RTL)/core/$(DCD).v $(DCD).sby f_idecode.v
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sby -f $(DCD).sby pipe_nodiv_nompy_nocis_nopipe
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$(DCD)_nopipe_nodiv_nompy_nocis_nopipe/PASS: $(RTL)/core/$(DCD).v $(DCD).sby f_idecode.v
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sby -f $(DCD).sby nopipe_nodiv_nompy_nocis_nopipe
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.PHONY: $(DMA)
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$(DMA): $(DMA)/PASS
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$(DMA)/PASS: $(RTL)/peripherals/$(DMA).v $(MASTER) $(SLAVE) $(DMA).sby
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sby -f $(DMA).sby
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.PHONY: $(ALU)
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$(ALU): $(ALU)/PASS
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$(ALU)/PASS: $(ALU).sby $(RTL)/core/$(ALU).v abs_mpy.v
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sby -f $(ALU).sby
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DCACHE_FILES := $(DCACHE).sby $(RTL)/core/dcache.v $(MASTER) $(RTL)/core/iscachable.v
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.PHONY: $(DCACHE)
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$(DCACHE) : $(DCACHE)_full/PASS $(DCACHE)_full_single/PASS $(DCACHE)_bare/PASS
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$(DCACHE) : $(DCACHE)_nolock_nolocal/PASS $(DCACHE)_nolock_system/PASS
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$(DCACHE) : $(DCACHE)_piped/PASS $(DCACHE)_cover/PASS $(DCACHE)_cover_pipe/PASS
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$(DCACHE)_full/PASS: $(DCACHE_FILES)
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sby -f $(DCACHE).sby full
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$(DCACHE)_full_single/PASS: $(DCACHE_FILES)
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sby -f $(DCACHE).sby full_single
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$(DCACHE)_bare/PASS: $(DCACHE_FILES)
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sby -f $(DCACHE).sby bare
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$(DCACHE)_nolock_nolocal/PASS: $(DCACHE_FILES)
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sby -f $(DCACHE).sby nolock_nolocal
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$(DCACHE)_nolock_system/PASS: $(DCACHE_FILES)
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sby -f $(DCACHE).sby nolock_system
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$(DCACHE)_piped/PASS: $(DCACHE_FILES)
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sby -f $(DCACHE).sby piped
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$(DCACHE)_cover/PASS: $(DCACHE_FILES)
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sby -f $(DCACHE).sby cover
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$(DCACHE)_cover_pipe/PASS: $(DCACHE_FILES)
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| 240 |
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sby -f $(DCACHE).sby cover_pipe
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| 241 |
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.PHONY: $(DIV)
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$(DIV) : $(DIV)/PASS
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$(DIV)/PASS: $(DIV).sby $(RTL)/core/div.v
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sby -f $(DIV).sby
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.PHONY: $(CPU)
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| 248 |
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$(CPU): $(CPU)_dcache/PASS $(CPU)_piped/PASS
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$(CPU): $(CPU)_nopipe/PASS $(CPU)_lowlogic/PASS $(CPU)_ice40/PASS
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CPUDEPS:= $(RTL)/core/$(CPU).v $(RTL)/core/cpuops.v $(RTL)/core/idecode.v \
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$(RTL)/core/pipemem.v $(RTL)/core/memops.v \
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| 252 |
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$(RTL)/ex/wbdblpriarb.v $(RTL)/ex/fwb_counter.v $(RTL)/cpudefs.v \
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f_idecode.v abs_div.v abs_prefetch.v abs_mpy.v $(MASTER) $(SLAVE) \
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| 254 |
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$(CPU).sby
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$(CPU)_dcache/PASS: $(CPUDEPS) $(RTL)/core/dcache.v $(RTL)/core/iscachable.v
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| 256 |
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sby -f $(CPU).sby dcache
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$(CPU)_piped/PASS: $(CPUDEPS)
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sby -f $(CPU).sby piped
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$(CPU)_nopipe/PASS: $(CPUDEPS)
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sby -f $(CPU).sby nopipe
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$(CPU)_lowlogic/PASS: $(CPUDEPS)
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sby -f $(CPU).sby lowlogic
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$(CPU)_ice40/PASS: $(CPUDEPS)
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sby -f $(CPU).sby ice40
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.PHONY: clean
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clean:
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rm -rf $(PFONE)*/ $(PFTWO)*/ $(PFCACHE)*/
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| 273 |
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rm -f $(WBDLY).smt2 $(WBDLY)*.vcd $(WBDLY).yslog
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| 274 |
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rm -f $(PRIARB).smt2 $(PRIARB)*.vcd $(PRIARB).yslog
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| 275 |
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rm -f $(DBL).smt2 $(DBL)*.vcd $(DBL).yslog
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| 276 |
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rm -rf $(MEM)*/ $(PIPE)*/ $(MMU)*/
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| 277 |
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rm -rf $(TMR)*/ $(CNT)*/ $(JIF)*/
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| 278 |
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rm -rf $(WDG)*/ $(INT)*/ $(DCD)_*/
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| 279 |
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rm -rf $(DMA)*/ $(ALU)*/ $(DIV)*/
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rm -rf $(DCACHE)_*/
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rm -rf $(CPU)_*/
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| 282 |
|
|
rm -f *.check
|
