Subversion Repositories zipcpu

module  mcve(i_clk, o_val);

        input   wire    i_clk;

        output  reg     o_val;

        parameter [0:0]   THE_TEST = 1'b0;

        generate if (THE_TEST)

        begin

                always @(*)

                        o_val = 1'b1;

                always @(*)

                        assert(o_val);

        end else begin

                always @(*)

                        o_val = 1'b0;

        end endgenerate

endmodule