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dgisselq |
################################################################################
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#
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# Filename: Makefile
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#
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# Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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#
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# Purpose: This makefile builds a verilator simulation of the zipsystem.
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# It does not make the system within Vivado or Quartus.
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#
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#
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# Creator: Dan Gisselquist, Ph.D.
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# Gisselquist Tecnology, LLC
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#
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################################################################################
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#
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# Copyright (C) 2015, Gisselquist Technology, LLC
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#
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# This program is free software (firmware): you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as published
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# by the Free Software Foundation, either version 3 of the License, or (at
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# your option) any later version.
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#
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# This program is distributed in the hope that it will be useful, but WITHOUT
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# ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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# for more details.
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#
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# License: GPL, v3, as defined and found on www.gnu.org,
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# http://www.gnu.org/licenses/gpl.html
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#
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#
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################################################################################
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#
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.PHONY: all
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all: zipsystem
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CORED:= core
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PRPHD:= peripherals
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AUXD := aux
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VSRC := zipsystem.v \
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$(PRPHD)/flashcache.v $(PRPHD)/icontrol.v \
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$(PRPHD)/zipcounter.v $(PRPHD)/zipjiffies.v \
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$(PRPHD)/ziptimer.v $(PRPHD)/ziptrap.v \
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$(CORED)/zipcpu.v $(CORED)/cpuops.v \
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$(CORED)/pipefetch.v $(CORED)/prefetch.v \
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$(CORED)/memops.v \
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$(AUXD)/busdelay.v $(AUXD)/wbarbiter.v
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VOBJ := obj_dir
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$(VOBJ)/Vzipsystem.cpp: $(VSRC)
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verilator -cc -y $(CORED)/ -y $(PRPHD) -y $(AUXD) zipsystem.v
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$(VOBJ)/Vzipsystem__ALL.a: $(VOBJ)/Vzipsystem.cpp $(VOBJ)/Vzipsystem.h
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cd $(VOBJ); make -f Vzipsystem.mk
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.PHONY: zipsystem
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zipsystem: $(VOBJ)/Vzipsystem__ALL.a
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.PHONY: clean
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clean:
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rm -rf $(VOBJ)
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