OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [core/] [cpuops.v] - Blame information for rev 5

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dgisselq
///////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    cpuops.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     
8
//
9
// Creator:     Dan Gisselquist, Ph.D.
10
//              Gisselquist Tecnology, LLC
11
//
12
///////////////////////////////////////////////////////////////////////////
13
//
14
// Copyright (C) 2015, Gisselquist Technology, LLC
15
//
16
// This program is free software (firmware): you can redistribute it and/or
17
// modify it under the terms of  the GNU General Public License as published
18
// by the Free Software Foundation, either version 3 of the License, or (at
19
// your option) any later version.
20
//
21
// This program is distributed in the hope that it will be useful, but WITHOUT
22
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
23
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
24
// for more details.
25
//
26
// License:     GPL, v3, as defined and found on www.gnu.org,
27
//              http://www.gnu.org/licenses/gpl.html
28
//
29
//
30
///////////////////////////////////////////////////////////////////////////
31
//
32
module  cpuops(i_clk, i_rst, i_ce, i_valid, i_op, i_a, i_b, o_c, o_f, o_valid);
33
        input           i_clk, i_rst, i_ce;
34
        input           [3:0]    i_op;
35
        input           [31:0]   i_a, i_b;
36
        input                   i_valid;
37
        output  reg     [31:0]   o_c;
38
        output  wire    [3:0]    o_f;
39
        output  reg             o_valid;
40
 
41
        wire    [63:0]   w_rol_tmp;
42
        assign  w_rol_tmp = { i_a, i_a } << i_b[4:0];
43
        wire    [31:0]   w_rol_result;
44
        assign  w_rol_result = w_rol_tmp[63:32]; // Won't set flags
45
 
46
        wire    z, n, v;
47
        reg     c, pre_sign, set_ovfl;
48
        always @(posedge i_clk)
49
                if (i_ce)
50
                        set_ovfl =((((i_op==4'h0)||(i_op==4'h8)) // SUB&CMP
51
                                                &&(i_a[31] != i_b[31]))
52
                                ||((i_op==4'ha)&&(i_a[31] == i_b[31])) // ADD
53
                                ||(i_op == 4'hd) // LSL
54
                                ||(i_op == 4'hf)); // LSR
55
        always @(posedge i_clk)
56
                if (i_ce)
57
                begin
58
                        pre_sign <= (i_a[31]);
59
                        c <= 1'b0;
60 3 dgisselq
                        casez(i_op)
61
                        4'b?000:{c,o_c } <= {(i_b>i_a),i_a - i_b};// CMP/SUB
62
                        4'b?001:   o_c   <= i_a & i_b;          // BTST/And
63 2 dgisselq
                        // 4'h4:   o_c   <= i_a[15:0] * i_b[15:0];
64
                        4'h5:      o_c   <= w_rol_result;       // ROL
65
                        4'h6:      o_c   <= { i_a[31:16], i_b[15:0] }; // LODILO
66
                        4'h7:      o_c   <= { i_b[15:0], i_a[15:0] }; // LODIHI
67
                        4'ha: { c, o_c } <= i_a + i_b;          // Add
68
                        4'hb:      o_c   <= i_a | i_b;          // Or
69
                        4'hc:      o_c   <= i_a ^ i_b;          // Xor
70
                        4'hd: { c, o_c } <= {1'b0, i_a } << i_b[4:0];    // LSL
71
                        4'he: { c, o_c } <= { i_a[31],i_a}>> (i_b[4:0]);// ASR
72
                        4'hf: { c, o_c } <= { 1'b0, i_a } >> (i_b[4:0]);// LSR
73
                        default:   o_c   <=       i_b;          // MOV, LDI
74
                        endcase
75
                end
76
 
77
        assign  z = (o_c == 32'h0000);
78
        assign  n = (o_c[31]);
79
        assign  v = (set_ovfl)&&(pre_sign != o_c[31]);
80
 
81
        assign  o_f = { v, n, c, z };
82
 
83
        initial o_valid = 1'b0;
84
        always @(posedge i_clk)
85
                if (i_rst)
86
                        o_valid <= 1'b0;
87
                else if (i_ce)
88
                        o_valid <= i_valid;
89
                else if (~i_ce)
90
                        o_valid <= 1'b0;
91
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.