URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [core/] [cpuops.v] - Blame information for rev 91

Go to most recent revision | Details | Compare with Previous | View Log


///////////////////////////////////////////////////////////////////////////
//
// Filename:    cpuops.v
//
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose:     This supports the instruction set reordering of operations
//              created by the second generation instruction set, as well as
//      the new operations of POPC (population count) and BREV (bit reversal).
//
//
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//
//
///////////////////////////////////////////////////////////////////////////
//
module  cpuops(i_clk,i_rst, i_ce, i_valid, i_op, i_a, i_b, o_c, o_f, o_valid,
                        o_illegal, o_busy);
        parameter       IMPLEMENT_MPY = 1;
        input           i_clk, i_rst, i_ce;
        input           [3:0]    i_op;
        input           [31:0]   i_a, i_b;
        input                   i_valid;
        output  reg     [31:0]   o_c;
        output  wire    [3:0]    o_f;
        output  reg             o_valid;
        output  wire            o_illegal;
        output  wire            o_busy;
 
        // Rotate-left pre-logic
        wire    [63:0]   w_rol_tmp;
        assign  w_rol_tmp = { i_a, i_a } << i_b[4:0];
        wire    [31:0]   w_rol_result;
        assign  w_rol_result = w_rol_tmp[63:32]; // Won't set flags
 
        // Shift register pre-logic
        wire    [32:0]           w_lsr_result, w_asr_result;
        assign  w_asr_result = (|i_b[31:5])? {(33){i_a[31]}}
                                : ( {i_a, 1'b0 } >>> (i_b[4:0]) );// ASR
        assign  w_lsr_result = (|i_b[31:5])? 33'h00
                                : ( { i_a, 1'b0 } >> (i_b[4:0]) );// LSR
 
        // Bit reversal pre-logic
        wire    [31:0]   w_brev_result;
        genvar  k;
        generate
        for(k=0; k<32; k=k+1)
        begin : bit_reversal_cpuop
                assign w_brev_result[k] = i_b[31-k];
        end endgenerate
 
        // Popcount pre-logic
        wire    [31:0]   w_popc_result;
        assign  w_popc_result[5:0]=
                 ({5'h0,i_b[ 0]}+{5'h0,i_b[ 1]}+{5'h0,i_b[ 2]}+{5'h0,i_b[ 3]})
                +({5'h0,i_b[ 4]}+{5'h0,i_b[ 5]}+{5'h0,i_b[ 6]}+{5'h0,i_b[ 7]})
                +({5'h0,i_b[ 8]}+{5'h0,i_b[ 9]}+{5'h0,i_b[10]}+{5'h0,i_b[11]})
                +({5'h0,i_b[12]}+{5'h0,i_b[13]}+{5'h0,i_b[14]}+{5'h0,i_b[15]})
                +({5'h0,i_b[16]}+{5'h0,i_b[17]}+{5'h0,i_b[18]}+{5'h0,i_b[19]})
                +({5'h0,i_b[20]}+{5'h0,i_b[21]}+{5'h0,i_b[22]}+{5'h0,i_b[23]})
                +({5'h0,i_b[24]}+{5'h0,i_b[25]}+{5'h0,i_b[26]}+{5'h0,i_b[27]})
                +({5'h0,i_b[28]}+{5'h0,i_b[29]}+{5'h0,i_b[30]}+{5'h0,i_b[31]});
        assign  w_popc_result[31:6] = 26'h00;
 
        // Prelogic for our flags registers
        wire    z, n, v;
        reg     c, pre_sign, set_ovfl;
        always @(posedge i_clk)
                if (i_ce) // 1 LUT
                        set_ovfl =(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP
                                ||((i_op==4'h2)&&(i_a[31] == i_b[31])) // ADD
                                ||(i_op == 4'h6) // LSL
                                ||(i_op == 4'h5)); // LSR
 
 
        // A 4-way multiplexer can be done in one 6-LUT.
        // A 16-way multiplexer can therefore be done in 4x 6-LUT's with
        //      the Xilinx multiplexer fabric that follows. 
        // Given that we wish to apply this multiplexer approach to 33-bits,
        // this will cost a minimum of 132 6-LUTs.
        generate
        if (IMPLEMENT_MPY == 0)
        begin
                always @(posedge i_clk)
                if (i_ce)
                begin
                        pre_sign <= (i_a[31]);
                        c <= 1'b0;
                        casez(i_op)
                        4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB
                        4'b0001:   o_c   <= i_a & i_b;          // BTST/And
                        4'b0010:{c,o_c } <= i_a + i_b;          // Add
                        4'b0011:   o_c   <= i_a | i_b;          // Or
                        4'b0100:   o_c   <= i_a ^ i_b;          // Xor
                        4'b0101:{o_c,c } <= w_lsr_result[32:0];  // LSR
                        4'b0110:{c,o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0];     // LSL
                        4'b0111:{o_c,c } <= w_asr_result[32:0];  // ASR
                        4'b1000:   o_c   <= { i_b[15: 0], i_a[15:0] }; // LODIHI
                        4'b1001:   o_c   <= { i_a[31:16], i_b[15:0] }; // LODILO
                        // 4'h1010: The unimplemented MPYU,
                        // 4'h1011: and here for the unimplemented MPYS
                        4'b1100:   o_c   <= w_brev_result;      // BREV
                        4'b1101:   o_c   <= w_popc_result;      // POPC
                        4'b1110:   o_c   <= w_rol_result;       // ROL
                        default:   o_c   <= i_b;                // MOV, LDI
                        endcase
                end
 
                assign o_busy = 1'b0;
 
                reg     r_illegal;
                always @(posedge i_clk)
                        r_illegal <= (i_ce)&&((i_op == 4'h3)||(i_op == 4'h4));
                assign o_illegal = r_illegal;
        end else begin
                //
                // Multiply pre-logic
                //
                wire    signed  [16:0]   w_mpy_a_input, w_mpy_b_input;
                wire            [33:0]   w_mpy_result;
                reg             [31:0]   r_mpy_result;
                assign  w_mpy_a_input ={ ((i_a[15])&(i_op[0])), i_a[15:0] };
                assign  w_mpy_b_input ={ ((i_b[15])&(i_op[0])), i_b[15:0] };
                assign  w_mpy_result   = w_mpy_a_input * w_mpy_b_input;
                always @(posedge i_clk)
                        if (i_ce)
                                r_mpy_result  = w_mpy_result[31:0];
 
                //
                // The master ALU case statement
                //
                always @(posedge i_clk)
                if (i_ce)
                begin
                        pre_sign <= (i_a[31]);
                        c <= 1'b0;
                        casez(i_op)
                        4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB
                        4'b0001:   o_c   <= i_a & i_b;          // BTST/And
                        4'b0010:{c,o_c } <= i_a + i_b;          // Add
                        4'b0011:   o_c   <= i_a | i_b;          // Or
                        4'b0100:   o_c   <= i_a ^ i_b;          // Xor
                        4'b0101:{o_c,c } <= w_lsr_result[32:0];  // LSR
                        4'b0110:{c,o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0];     // LSL
                        4'b0111:{o_c,c } <= w_asr_result[32:0];  // ASR
                        4'b1000:   o_c   <= { i_b[15: 0], i_a[15:0] }; // LODIHI
                        4'b1001:   o_c   <= { i_a[31:16], i_b[15:0] }; // LODILO
                        4'b1010:   o_c   <= r_mpy_result; // MPYU
                        4'b1011:   o_c   <= r_mpy_result; // MPYS
                        4'b1100:   o_c   <= w_brev_result;      // BREV
                        4'b1101:   o_c   <= w_popc_result;      // POPC
                        4'b1110:   o_c   <= w_rol_result;       // ROL
                        default:   o_c   <= i_b;                // MOV, LDI
                        endcase
                end else if (r_busy)
                        o_c <= r_mpy_result;
 
                reg     r_busy;
                initial r_busy = 1'b0;
                always @(posedge i_clk)
                        r_busy <= (~i_rst)&&(i_ce)&&(i_valid)
                                        &&(i_op[3:1] == 3'h5);
 
                assign o_busy = r_busy;
 
                assign o_illegal = 1'b0;
        end endgenerate
 
        assign  z = (o_c == 32'h0000);
        assign  n = (o_c[31]);
        assign  v = (set_ovfl)&&(pre_sign != o_c[31]);
 
        assign  o_f = { v, n, c, z };
 
        initial o_valid = 1'b0;
        always @(posedge i_clk)
                if (i_rst)
                        o_valid <= 1'b0;
                else
                        o_valid <= (i_ce)&&(i_valid)&&(i_op[3:1] != 3'h5)
                                        ||(o_busy);
endmodule

Line No.	Rev	Author	Line
1	2	dgisselq	`///////////////////////////////////////////////////////////////////////////`
2			`//`
3			`// Filename: cpuops.v`
4			`//`
5			`// Project: Zip CPU -- a small, lightweight, RISC CPU soft core`
6			`//`
7	69	dgisselq	`// Purpose: This supports the instruction set reordering of operations`
8			`// created by the second generation instruction set, as well as`
9			`// the new operations of POPC (population count) and BREV (bit reversal).`
10	2	dgisselq	`//`
11	69	dgisselq	`//`
12	2	dgisselq	`// Creator: Dan Gisselquist, Ph.D.`
13	69	dgisselq	`// Gisselquist Technology, LLC`
14	2	dgisselq	`//`
15			`///////////////////////////////////////////////////////////////////////////`
16			`//`
17			`// Copyright (C) 2015, Gisselquist Technology, LLC`
18			`//`
19			`// This program is free software (firmware): you can redistribute it and/or`
20			`// modify it under the terms of the GNU General Public License as published`
21			`// by the Free Software Foundation, either version 3 of the License, or (at`
22			`// your option) any later version.`
23			`//`
24			`// This program is distributed in the hope that it will be useful, but WITHOUT`
25			`// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
26			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
27			`// for more details.`
28			`//`
29			`// License: GPL, v3, as defined and found on www.gnu.org,`
30			`// http://www.gnu.org/licenses/gpl.html`
31			`//`
32			`//`
33			`///////////////////////////////////////////////////////////////////////////`
34			`//`
35	69	dgisselq	`module cpuops(i_clk,i_rst, i_ce, i_valid, i_op, i_a, i_b, o_c, o_f, o_valid,`
36	71	dgisselq	`o_illegal, o_busy);`
37	56	dgisselq	`parameter IMPLEMENT_MPY = 1;`
38	2	dgisselq	`input i_clk, i_rst, i_ce;`
39			`input [3:0] i_op;`
40			`input [31:0] i_a, i_b;`
41			`input i_valid;`
42			`output reg [31:0] o_c;`
43			`output wire [3:0] o_f;`
44			`output reg o_valid;`
45	56	dgisselq	`output wire o_illegal;`
46	71	dgisselq	`output wire o_busy;`
47	2	dgisselq
48	62	dgisselq	`// Rotate-left pre-logic`
49	2	dgisselq	`wire [63:0] w_rol_tmp;`
50			`assign w_rol_tmp = { i_a, i_a } << i_b[4:0];`
51			`wire [31:0] w_rol_result;`
52			`assign w_rol_result = w_rol_tmp[63:32]; // Won't set flags`
53	62	dgisselq
54			`// Shift register pre-logic`
55	56	dgisselq	`wire [32:0] w_lsr_result, w_asr_result;`
56			`assign w_asr_result = (\|i_b[31:5])? {(33){i_a[31]}}`
57			`: ( {i_a, 1'b0 } >>> (i_b[4:0]) );// ASR`
58			`assign w_lsr_result = (\|i_b[31:5])? 33'h00`
59			`: ( { i_a, 1'b0 } >> (i_b[4:0]) );// LSR`
60	2	dgisselq
61	69	dgisselq	`// Bit reversal pre-logic`
62			`wire [31:0] w_brev_result;`
63			`genvar k;`
64			`generate`
65			`for(k=0; k<32; k=k+1)`
66	80	dgisselq	`begin : bit_reversal_cpuop`
67	69	dgisselq	`assign w_brev_result[k] = i_b[31-k];`
68	80	dgisselq	`end endgenerate`
69	25	dgisselq
70	69	dgisselq	`// Popcount pre-logic`
71			`wire [31:0] w_popc_result;`
72			`assign w_popc_result[5:0]=`
73			`({5'h0,i_b[ 0]}+{5'h0,i_b[ 1]}+{5'h0,i_b[ 2]}+{5'h0,i_b[ 3]})`
74			`+({5'h0,i_b[ 4]}+{5'h0,i_b[ 5]}+{5'h0,i_b[ 6]}+{5'h0,i_b[ 7]})`
75			`+({5'h0,i_b[ 8]}+{5'h0,i_b[ 9]}+{5'h0,i_b[10]}+{5'h0,i_b[11]})`
76			`+({5'h0,i_b[12]}+{5'h0,i_b[13]}+{5'h0,i_b[14]}+{5'h0,i_b[15]})`
77			`+({5'h0,i_b[16]}+{5'h0,i_b[17]}+{5'h0,i_b[18]}+{5'h0,i_b[19]})`
78			`+({5'h0,i_b[20]}+{5'h0,i_b[21]}+{5'h0,i_b[22]}+{5'h0,i_b[23]})`
79			`+({5'h0,i_b[24]}+{5'h0,i_b[25]}+{5'h0,i_b[26]}+{5'h0,i_b[27]})`
80			`+({5'h0,i_b[28]}+{5'h0,i_b[29]}+{5'h0,i_b[30]}+{5'h0,i_b[31]});`
81			`assign w_popc_result[31:6] = 26'h00;`
82
83			`// Prelogic for our flags registers`
84	2	dgisselq	`wire z, n, v;`
85			`reg c, pre_sign, set_ovfl;`
86			`always @(posedge i_clk)`
87	69	dgisselq	`if (i_ce) // 1 LUT`
88			`set_ovfl =(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP`
89			`\|\|((i_op==4'h2)&&(i_a[31] == i_b[31])) // ADD`
90			`\|\|(i_op == 4'h6) // LSL`
91			`\|\|(i_op == 4'h5)); // LSR`
92	56	dgisselq
93	62	dgisselq
94			`// A 4-way multiplexer can be done in one 6-LUT.`
95			`// A 16-way multiplexer can therefore be done in 4x 6-LUT's with`
96			`// the Xilinx multiplexer fabric that follows.`
97			`// Given that we wish to apply this multiplexer approach to 33-bits,`
98			`// this will cost a minimum of 132 6-LUTs.`
99	56	dgisselq	`generate`
100			`if (IMPLEMENT_MPY == 0)`
101			`begin`
102			`always @(posedge i_clk)`
103	2	dgisselq	`if (i_ce)`
104			`begin`
105			`pre_sign <= (i_a[31]);`
106			`c <= 1'b0;`
107	3	dgisselq	`casez(i_op)`
108	69	dgisselq	`4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB`
109			`4'b0001: o_c <= i_a & i_b; // BTST/And`
110			`4'b0010:{c,o_c } <= i_a + i_b; // Add`
111			`4'b0011: o_c <= i_a \| i_b; // Or`
112			`4'b0100: o_c <= i_a ^ i_b; // Xor`
113			`4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR`
114			`4'b0110:{c,o_c } <= (\|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL`
115			`4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR`
116			`4'b1000: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI`
117			`4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO`
118			`// 4'h1010: The unimplemented MPYU,`
119			`// 4'h1011: and here for the unimplemented MPYS`
120			`4'b1100: o_c <= w_brev_result; // BREV`
121			`4'b1101: o_c <= w_popc_result; // POPC`
122			`4'b1110: o_c <= w_rol_result; // ROL`
123			`default: o_c <= i_b; // MOV, LDI`
124	56	dgisselq	`endcase`
125			`end`
126	71	dgisselq
127			`assign o_busy = 1'b0;`
128
129			`reg r_illegal;`
130			`always @(posedge i_clk)`
131			`r_illegal <= (i_ce)&&((i_op == 4'h3)\|\|(i_op == 4'h4));`
132			`assign o_illegal = r_illegal;`
133	56	dgisselq	`end else begin`
134	62	dgisselq	`//`
135			`// Multiply pre-logic`
136			`//`
137	80	dgisselq	`wire signed [16:0] w_mpy_a_input, w_mpy_b_input;`
138	71	dgisselq	`wire [33:0] w_mpy_result;`
139			`reg [31:0] r_mpy_result;`
140			`assign w_mpy_a_input ={ ((i_a[15])&(i_op[0])), i_a[15:0] };`
141			`assign w_mpy_b_input ={ ((i_b[15])&(i_op[0])), i_b[15:0] };`
142			`assign w_mpy_result = w_mpy_a_input * w_mpy_b_input;`
143			`always @(posedge i_clk)`
144			`if (i_ce)`
145			`r_mpy_result = w_mpy_result[31:0];`
146	56	dgisselq
147	62	dgisselq	`//`
148			`// The master ALU case statement`
149			`//`
150	56	dgisselq	`always @(posedge i_clk)`
151			`if (i_ce)`
152			`begin`
153			`pre_sign <= (i_a[31]);`
154			`c <= 1'b0;`
155			`casez(i_op)`
156	69	dgisselq	`4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB`
157			`4'b0001: o_c <= i_a & i_b; // BTST/And`
158			`4'b0010:{c,o_c } <= i_a + i_b; // Add`
159			`4'b0011: o_c <= i_a \| i_b; // Or`
160			`4'b0100: o_c <= i_a ^ i_b; // Xor`
161			`4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR`
162			`4'b0110:{c,o_c } <= (\|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL`
163			`4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR`
164			`4'b1000: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI`
165			`4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO`
166	71	dgisselq	`4'b1010: o_c <= r_mpy_result; // MPYU`
167			`4'b1011: o_c <= r_mpy_result; // MPYS`
168	69	dgisselq	`4'b1100: o_c <= w_brev_result; // BREV`
169			`4'b1101: o_c <= w_popc_result; // POPC`
170			`4'b1110: o_c <= w_rol_result; // ROL`
171			`default: o_c <= i_b; // MOV, LDI`
172	2	dgisselq	`endcase`
173	71	dgisselq	`end else if (r_busy)`
174			`o_c <= r_mpy_result;`
175	2	dgisselq
176	71	dgisselq	`reg r_busy;`
177			`initial r_busy = 1'b0;`
178	56	dgisselq	`always @(posedge i_clk)`
179	71	dgisselq	`r_busy <= (~i_rst)&&(i_ce)&&(i_valid)`
180			`&&(i_op[3:1] == 3'h5);`
181
182			`assign o_busy = r_busy;`
183
184	56	dgisselq	`assign o_illegal = 1'b0;`
185	71	dgisselq	`end endgenerate`
186	56	dgisselq
187	2	dgisselq	`assign z = (o_c == 32'h0000);`
188			`assign n = (o_c[31]);`
189			`assign v = (set_ovfl)&&(pre_sign != o_c[31]);`
190
191			`assign o_f = { v, n, c, z };`
192
193			`initial o_valid = 1'b0;`
194			`always @(posedge i_clk)`
195			`if (i_rst)`
196			`o_valid <= 1'b0;`
197	56	dgisselq	`else`
198	71	dgisselq	`o_valid <= (i_ce)&&(i_valid)&&(i_op[3:1] != 3'h5)`
199			`\|\|(o_busy);`
200	2	dgisselq	`endmodule`

Browse

Tools

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [core/] [cpuops.v] - Blame information for rev 91